RU2474004C1 - Method to manufacture multi-level thin-film microcircuit chips - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: in the method to manufacture multi-level thin-film microcircuit chips, including alternate vacuum application of conductor layers onto a substrate with subsequent development of a pattern of a chip by the method of photolithography, application of insulating layers and formation of level-to-level connections in them from one conductor layer to another by etching transition windows in the insulation and their dusting with a conducting material, level-to-level connections are formed by dusting of transition windows simultaneously by sputtering of the conductor layer of the appropriate level and making a pattern of the chip by the method of photolithography, besides, level-to-level connections are formed of a larger size than the size of transition windows in plan. In each subsequent insulating layer they etch transition windows of a larger size compared to the previous one.

EFFECT: simplified technology to make microcircuit chips and their higher reliability.

2 cl, 2 dwg

Description

 The invention relates to the field of manufacturing microcircuits and can be used for the manufacture of multi-level thin-film hybrid integrated circuits (GIS) and anisotropic magnetoresistive converters (AMRP).

One of the main problems of multilevel microcircuit technology is the creation of reliable electrical contact between conductors separated by an insulating layer.

The well-known "Method of manufacturing a thin-film microcircuit" described in patent RU 2040131 C1 class. Н05К 3/46, in which this task for a two-level GIS is solved as follows. A V-Cu-V structure is sprayed in a vacuum on a polycor substrate, on which a pattern of conductors and contact pads is formed by photolithography. Then AD-9103 polyimide varnish is applied, which is imidized by aging at elevated temperature. On the insulation layer thus obtained, photolithography etch transition windows in the places of inter-level joints. After etching of the upper layer V in the window, copper is galvanically deposited onto exposed copper to the window is completely filled (the so-called planarization process - surface leveling). V-Cu is precipitated from above, photolithography is performed and constructive protection is formed.

The disadvantage of this method is the complexity of the process and the inability to use it for the manufacture of microcircuits with a number of levels of more than two. In addition, it is technically difficult at the same time in all transition windows to galvanically grow copper precisely to their upper level (polyimide surface). Due to the natural unevenness of the electric field and the depletion of the solution during operation, the galvanic copper will be either above or below the upper level of the window, which reduces the reliability of switching due to the limited contact of the conductive layer with the copper "column".

Also known is “A method of manufacturing microboards with multi-level thin-film switching” No. 2 398369 cells. H05K 3/00 from 08/24/09, selected by us for the prototype.

The method consists in the fact that nickel is etched in the first level, consisting of V-Cu-Ni, and tin is deposited chemically on the opened copper, and then Ti-Cu-Ti films are deposited by vacuum deposition through a magnetic mask with a topological inter-level switching pattern. obtaining a planar structure.

This solution is the simplest compared to the previous one, however, it has several disadvantages.

Firstly, the use of tin, designed to reduce the transition resistance, has limited use, because it does not withstand high temperatures during the further formation of the microcircuit. In addition, if the tin layer is included in the structure of the contact pad, then welding of gold wire is impossible to it.

Secondly, the use of magnetic masks for dusting windows requires additional material costs. During operation, dusting of the masks occurs, as a result of which the size of the windows changes. In the case of inaccurate alignment, on the one hand, the transition window may not be filled, which reduces the reliability of electrical contact, and on the other hand, a protrusion is deposited on the insulating polyimide, which can violate the following insulation. The planarization process occurs with a large error, because thermal spraying from the evaporator is rather roughly controlled by the thickness of the sprayed film.

The technical result of the proposed solution is to simplify the manufacturing technology of microcircuits and increase their reliability.

The technical result is achieved by the fact that in the method of manufacturing multilevel thin-film microcircuits, which includes alternating vacuum deposition of conductive layers on a substrate, followed by photolithography drawing a circuit, applying insulating layers and forming inter-level compounds in them from one conductive layer to another by etching transition windows in insulation and spraying them with conductive material, inter-level connections are formed by spraying transition windows simultaneously with spraying iem appropriate level conductor layer circuit pattern and manufacturing method of photolithography, the interlevel connections are formed larger than the size in terms of transition windows.

In each subsequent insulating layer, larger transition windows are etched than in the previous one.

The invention is illustrated by drawings.

Figure 1 (a, b, c) shows the structure of a multi-level thin-film microcircuit according to the proposed method.

In figure 1 (a, b, c):

1 - substrate;

2 - the first conductor layer;

3 - contact area of the first conductive layer;

4 - the first insulating layer;

5 - transition window in the first insulating layer;

6 - the second conductor layer;

7 - contact area of the second conductive layer;

8 - interlayer connection between the first and second conductive layers;

9 - step inter-level connection 8;

10 - the rim of the inter-level connection 8;

11 - second insulating layer;

12 - transition window in the second insulating layer;

13 - the third conductor layer;

14 - contact area of the third conductor layer;

15 is an inter-level connection between the first, second and third conductive layers;

16 - step inter-level connection 15;

17 - the rim of the inter-level connection 15;

18 - constructive protection.

Figure 2 shows the topology of the functional layers of AMRP (three-layer conductor structure).

On figa shows the Winston bridge (the first functional element):

3 - contact pads of the first conductor layer (for Winston Bridge);

19 - magnetoresistive strips;

20 - jumpers;

21 - conductors.

On figb shows the first and second functional elements:

3 - contact pads of the first conductor layer (for Winston Bridge);

7 - contact pads of the second conductive layer (for the set / reset coil);

8 - interlayer connection between the first and second conductive layers;

22 - turns of a thin-film set / reset inductance coil (second functional element).

On figv shows the Winston bridge (first functional element), inductors "set / reset" (second functional element) and "offset" (third functional element):

3 - contact pads of the first conductor layer (for Winston Bridge);

7 - contact pads of the second conductive layer (for the set / reset coil);

8 - interlayer connection between the first and second conductive layers;

14 - contact pads of the third conductive layer (for the coil "offset");

15 is an inter-level connection between the first, second and third conductive layers;

23 - turns of a thin-film “inductance” inductor (third functional element).

The manufacturing process of a multi-level thin-film micro-circuit board (figure 1) is as follows:

- cleaning the substrate from glass 1 (figa, b, c);

- spraying the first conductor layer 2 (figa, b, c);

- the formation by the method of photolithography pattern of the circuit and the contact pads 3 (figa) of the first conductive layer;

- applying the first insulating layer 4 (figa) and its imidization by heat treatment;

- the formation by the method of photolithography of transition windows 5 (figb) in the insulating layer 4 (figb);

- spraying the second conductor layer 6 (figa, b, c);

- the formation by photolithography of a pattern of the circuit, the contact pads of the second conductor layer 7 (Fig. 1b), inter-level connections 8 (Fig. 1b, c) between the first and second conductor layers. The size of the template is due to the presence of a conductor layer on the wall of the transition window 5 (Fig. 1b) in the form of a step 9 (Fig. 1b, c) of inter-level connection 8 (Fig. 1b, c) and on the surface of the insulating layer 4 (Fig. 1b) in the form rim 10 (figb, c);

- applying a second insulating layer 11 (figa, b, c) and its imidization by heat treatment;

- the formation by the method of photolithography of transition windows 12 (figv) in the insulating layer 11 (figv);

- spraying the third conductor layer 13 (Fig. 1 a, b, c) and forming by photolithography a pattern of the circuit, contact pads 14 (Fig. 1 c) of the third conductor layer, inter-level connections 15 (Fig. 1 c) between the first 2, second 6 and third 13 conductor layers. The size of the template is due to the presence of a conductor layer on the wall of the transition window 12 (Fig. 1c) in the form of a step 16 (Fig. 1c) of the interlayer connection 15 (Fig. 1c), and on the surface of the insulating layer 11 (Fig. 1c) in the form of a rim 17 ( figv);

- application of structural protection 18 (figa, b, c), in addition to the contact pads of the first conductor layer 3, the second conductor layer 7 and the third conductor layer 14.

After each technological operation, interoperational cleaning was carried out.

An example implementation of the method

The method was implemented in the manufacture of a three-layer microcircuit of a magnetoresistive sensitive element (MRE), shown in figure 2, consisting of three conductive (functional) elements a, b, c. The structure of a multi-level thin-film microcircuit according to the proposed method is shown in figa, b, c.

For the convenience of assembly and installation work, all contact pads of functional elements are formed directly on the surface of the substrate along the periphery of the pattern of conductive (functional) elements. The relationship between the functional elements and derived for them by the contact pads on the periphery of the figure is carried out by the proposed method.

The first conductor layer was obtained by vacuum deposition of permalloy at a thickness of 50 nm and the formation of magnetoresistive strips by photolithography method 19 of Figure 2a, V-Cu-Ni deposition of a thickness of 0.3 to 0.5 μm and the formation of jumpers 20 of fig. 2a by method of photolithography, conductors 21 fig.2a and contact pads 3 fig.1a.

Thus, in the photomask for the first conductor level 2 of Fig. 1a, it is planned to simultaneously form the Winston bridge, conductors and contact pads brought to the periphery of the figure.

The first insulating layer 4 of Fig. 1a was applied to the obtained structure from AD-9103 polyimide varnish with a thickness of 2 to 3 μm and transition windows 5 of Fig. 1b were formed in it. In Figure 2, the insulating layer is not shown.

The second conductor layer 6 Fig. 1 a, b, c was obtained by vacuum deposition of V-Cu-Ni with a thickness of 2 to 3 μm and the formation of:

- turns of a thin-film set / reset inductor 22 fig.2b (6, fig.1);

- inter-level connections 8 fig. 1b between the first 2 fig. 1 and the second 6 fig. 1 conductor layers;

- contact pads 7 Fig. 1b.

The connection between the first and second conductor layers was formed by etching in the first insulating layer 4 Fig. 1 of the transition window 5 Fig. 1b and spraying it simultaneously with the deposition of the second conductor layer 6 Fig. 1. The connection of the contact pad 7 Fig. 1b, formed for the second functional element - the set / reset inductor, was carried out through the inter-level connection 8 Fig. 1b. In this case, a photolithography method was used to create a pattern so that:

- in the first conductor layer, the fragment of the pattern against the window was 400 × 400 microns;

- the window size in the insulating layer 4 of Fig. 1 was 350 × 350 μm;

- in the second conductor layer around the transition window 5 of Fig. 1b, a rim of 10 Fig. 1b with a width of 50 μm from V-Cu-Ni was created.

Thus, the second conductor layer 6 of Fig. 1 through the inter-level connection 8 of Fig. 1 and the conductor formed at the first conductor level are connected to the contact pad 7 of Fig. 1, brought to the periphery of the figure, for the second functional element - inductor “set / reset ".

A second insulating layer 11 of Fig. 1 from AD-9103 polyimide varnish, 3 to 4 μm thick, was applied to the obtained structure, and transition windows of 12 Fig. 1 c were formed in it. In Figure 2, the insulation layer 11 of Figure 1 is not shown.

The third conductor layer 13 of Fig. 1 was obtained by vacuum deposition of V-Cu-Ni with a thickness of 2 to 3 μm and the formation of:

- thin-film inductance “offset” 23 fig. 2c, (13 fig. 1);

- inter-level connections 15 Fig. 1c between the first 2 Fig. 1c, the second 6 Fig. 1c and the third 13 Fig. 1 in the conductor layers;

- pads 14 fig. 1c for the “offset” inductor 23 fig. 2c.

The connection between the first, second, and third conductor layers was formed by etching in the second insulating layer 11 Fig. 1c of the transition window 12 Fig. 1c and spraying it simultaneously with the deposition of the second conductor layer 13 Fig. 1c. The contact of the contact pad 14 Fig. 1c was carried out through the inter-level connection 15 Fig. 1c. In this case, a photolithography method was used to create a pattern so that:

- in the first conductor layer, a fragment of the pattern against the transition window 5 of Fig. 1b was 400 × 400 microns;

- the window size in the insulating layer 4 of Fig. 1 was 350 × 350 μm;

- when the conductors of the second conductor layer are formed around the insulating window 5 of Fig. 1b, a rim of a width of 50 μm is formed;

- the size of the transition window 12 of Fig. 1c was 375 × 375 μm;

- in the third conductor layer around the transition window 12 of Fig. 1c, a rim of 17 Fig. 1 was created with a width of 25 μm from V-Cu-Ni.

Thus, the third conductor layer 13 Fig. 1c through inter-level connections 8 Fig. 1c and 15 Fig. 1c and the conductor formed in the first conductor layer 2 of Fig. 1 are connected to the contact area 14 of Fig. 1c, brought to the periphery of the figure, for The third functional element is the “offset” inductor.

Thus, the transition window 12 Fig. 1c between the “offset” coil of 23 Fig. 2c and the first conductor layer had inter-level connections in the form of a cascade (MSC) and represented an extremely reliable design.

The number of levels interconnected in the form of a cascade of connections can be arbitrarily large and is limited by the allowable window size at the upper level.

Transition windows are preferable to make round cross-section for more reliable spraying. We used transitional windows of a hexagonal shape, which, after etching, had a rounded shape. Etching of polyimide during the formation of transition windows is an isotropic process, as a result of which the window walls have a slope of about 45 °, which facilitates their dusting. Magnetron sputtering was used to spray transition windows.

Samples made by the above method were tested for adhesion and contact resistance of the contacts. Adhesion was determined by tearing off a welded joint of a gold wire with a diameter of 50 μm with a CP. The separation force was more than 22 g and occurred by breaking the wire without damaging the gearbox. The transition resistance between the bottom of the transition window and the last conductor level was less than 0.1 ohms.

Claims (2)

1. A method of manufacturing multilevel thin-film microcircuits, including alternating vacuum deposition of conductive layers on a substrate, followed by photolithography using a circuit diagram, applying insulating layers and forming inter-level compounds in them from one conductive layer to another by etching transition windows in insulation and spraying them with conductive material characterized in that the inter-level connections are formed by sputtering the transition windows simultaneously with the sputtering of the conductor layer I and the appropriate level of production of circuit pattern by photolithography, and the interlevel connections are formed larger than the size in terms of transition windows. 2. The method according to claim 1, characterized in that in each subsequent insulating layer, transition windows of a larger size are etched than in the previous one.

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