JP2010080551A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing occurrence of wiring pattern peeling and dishing at the time of flattening by CMP for stable production and capable of suppressing dropping of Q value of an inductance element which accompanies occurrence of eddy currents in a dummy pattern. <P>SOLUTION: A semiconductor device 10 includes a substrate, a dummy pattern 16 which is formed on the substrate to control a chemical-mechanical polishing step (CMP), and an inductance element 15 formed in spiral on the substrate. A dummy pattern 16 P is formed in the shape of polygon in top view that includes eight projections Ap of an acute angle at respective apexes. Since the eddy currents generated respectively along the edges on both sides sandwiching the tip of projection are directed opposite to each other, they are offset and negated with no development to a large eddy current. Since the route of eddy currents flowing along the edge part is longer, the resistance increases, and the area in which the eddy currents flow is reduced for suppressing eddy currents. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device such as a thin film integrated circuit including an inductance element spirally formed on a substrate and other multilayer wiring.

Conventionally, there has been proposed a semiconductor device including an inductance element and other various circuit elements in an integrated circuit. For example, an inductance element that obtains a desired inductance by a structure in which spiral spiral wiring is formed on a substrate and a capacitor element that accumulates electric charge by a structure in which conductors, dielectrics, and conductors are laminated are created in the circuit. The function is expressed.
The prior art column of Patent Document 1 describes that when a semiconductor device including the above-described inductance element is manufactured, planarization is performed by CMP (Chemical Physical Polishing Process). Further, when flattening by CMP, so-called dishing in which only wide wiring portions are intensively cut, peeling of fine wiring patterns, and the like are likely to occur. In order to avoid these problems, a dummy pattern has been conventionally arranged around the wiring pattern. Here, the dummy pattern means a pattern which is formed of the same material as the wiring pattern and exists independently without being connected to the circuit. When forming an inductance element in a multilayer wiring process including CMP in a circuit of a semiconductor device, a dummy pattern made of metal is arranged in a peripheral area of the inductance element so as to have a predetermined coverage for the above reason. A method has been proposed.

As shown in FIG. 13, Patent Document 1 proposes a structure that prevents deterioration of the characteristic (Q value) of the inductance element 215 when the dummy pattern region 212 is formed. Specifically, in the spiral inductor 210 having the spiral linear conductive layer 215a on the substrate 211, the upper surface is a dummy pattern for controlling the CMP process in a region excluding the region immediately below the linear conductive layer 215a. A groove for element isolation is formed on the substrate surface so that a convex portion is formed so as to be the region 212.
However, when an inductance element is created in the circuit of the semiconductor device together with the dummy pattern, capacitive coupling due to parasitic capacitance occurs between the dummy pattern and the wiring of the inductance element. As a result, eddy currents are induced in the dummy pattern and the substrate, and the high frequency characteristics, particularly the Q value, of the inductance element deteriorate.

In order to solve the above problems, Patent Document 2 has a plurality of substantially key-shaped dummy patterns in which at least one side of a closed loop is open in the vicinity of a spiral inductor formed inside the IC, although not shown in the document. Therefore, it has been proposed to prevent the deterioration of the Q value of the high-frequency characteristics of the spiral inductor.
JP 2002-110908 A JP 2007-273577 A

In the semiconductor device including the spiral inductor described in the former background art, the Q value of the inductance element is, for example, 10 when the substantially square-shaped dummy pattern is provided in order to suppress the occurrence of dishing and wiring pattern peeling. There was a problem of deterioration by about%.
Further, in the semiconductor device described in the latter background art, since an eddy current is generated along the edge of the dummy pattern inside the dummy pattern, there is a problem that the effect of suppressing the deterioration of the Q value cannot be sufficiently obtained. there were.

The present invention focuses on the above points, and its purpose is to suppress the occurrence of eddy currents inside the dummy pattern while suppressing the occurrence of dishing and wiring pattern peeling by providing the dummy pattern. Another object of the present invention is to provide a semiconductor device capable of suppressing deterioration of the Q value of an inductance element.

In order to achieve the above object, a semiconductor device according to the present invention includes (1) a substrate, a dummy pattern formed on the substrate for controlling a chemical mechanical polishing process, and a spiral formed on the substrate. In a semiconductor device having an inductor element,
The dummy pattern has a polygonal shape having a plurality of protrusions with sharp edges. (Hereinafter referred to as the first technical means of the present invention.)

  One of the main forms of the semiconductor device is (2) a plurality of the dummy patterns are arranged at predetermined intervals. (Hereinafter referred to as the second technical means of the present invention.)

The operation of the first technical means is as follows. That is, the dummy pattern has a polygonal plan view shape having a plurality of projections with sharp edges at the tip. For this reason, the eddy current generated along the edges on both sides of the tip of the protrusion at the protrusion portion of the dummy pattern has the effect of preventing the occurrence of dishing and wiring pattern peeling as in the conventional dummy pattern. Since the directions of are almost opposite, they cancel each other. In addition, since the dummy pattern has a plurality of protrusions, the resistance of the eddy current flowing along the edge increases, and the resistance increases and the area through which the eddy current flows decreases. it can.

The operation of the second technical means is as follows. That is, a plurality of the dummy patterns are arranged at a predetermined interval. Therefore, it is possible to provide a semiconductor element that can be stably produced without causing dishing or wiring pattern peeling.

The above and other objects, features, and advantages of the present invention will be apparent from the following detailed description and the accompanying drawings.

  According to the semiconductor device of the present invention, the occurrence of dishing and wiring pattern peeling at the time of planarization using CMP is generated along a plurality of edge portions on both sides sandwiching the tip in a plurality of projections with sharp tips. The directions of eddy currents are almost reversed and cancel each other. Further, since the path of the eddy current flowing along the edge is increased, the resistance is increased and the area through which the eddy current flows is reduced, so that the eddy current can be suppressed. For this reason, the eddy current generated inside the dummy pattern can be significantly suppressed, so that a decrease in the Q value of the inductance element can be suppressed, and a Q value equivalent to that when the dummy pattern is not provided can be obtained.

  Next, a first embodiment of the semiconductor device of the present invention will be described with reference to FIGS. FIG. 1 is a plan view for explaining the outline of the semiconductor device 10 of the first embodiment. FIG. 2 is a vertical cross-sectional view taken along line AA of FIG. 1 for explaining the internal structure of the semiconductor device 10 of the present embodiment. FIG. 3 is a longitudinal sectional view taken along line BB of FIG. 1 for explaining the internal structure of the semiconductor device 10 of the present embodiment. FIG. 4 is a diagram showing an example of current distribution in the dummy pattern of the semiconductor device of this embodiment.

As shown in FIGS. 1 to 3, a semiconductor device 10 according to the first embodiment includes a substrate 11 and a dummy for controlling a chemical mechanical polishing process (hereinafter referred to as CMP) formed on the substrate 11. A pattern 16 and an inductance element 15 spirally formed on the substrate 11 are included.
More specifically, in the semiconductor device 10, interlayer insulating films 12 a, 12 b, 12 c and insulating layers 13 a, 13 b, 13 c are alternately stacked in three layers on one main surface side of the substrate 11. Further, a protective layer 14 is laminated thereon.
In the first insulating layer 13a, a plurality of dummy patterns 16a are arranged at a predetermined interval. The second insulating layer 13b has a spiral lower layer wiring 15a constituting the spiral inductance element 15, and a plurality of dummy patterns arranged at predetermined intervals around the lower layer wiring 15a as described above. 16b. The third insulating layer 13c includes a spiral upper layer wiring 15c constituting the spiral inductance element 15, an extraction upper layer wiring 15d, and a predetermined area around the upper layer wirings 15c and 15d as described above. A plurality of dummy patterns 16c arranged at intervals of. Further, two via connection portions are formed in the third interlayer insulating film 12c so as to connect the spiral lower layer wiring 15a to the spiral upper layer wiring 15c and the upper layer wiring 15d of the lead portion. ing.
A plurality of terminal electrodes 17 are disposed on the protective layer 14 at a predetermined interval.
In the spirally formed inductance element 15, the outer peripheral end of the spiral upper layer wiring 15 c is connected to one of the plurality of terminal electrodes 17. Further, the end portion on the inner peripheral side of the spiral upper layer wiring 15c is connected to the end portion on the inner peripheral side of the spiral lower layer wiring 15a through a via connection portion 15b. An end portion on the outer peripheral side of the spiral lower layer wiring 15a is connected to one end side of an upper layer wiring 15d for extraction through a via connection portion 15b, and the other end of the upper layer wiring 15d is connected to the plurality of terminal electrodes 17. Connected to the other one.

In the semiconductor device 10 of this embodiment, the dummy patterns 16, 16a, 16b, and 16c are formed so as to have a polygonal plan view shape having a plurality of (for example, eight) protrusions Ap each having a sharp tip. Has been. As an example of the current distribution in the dummy pattern, the current distribution in the dummy pattern 16P located inside the spiral inductance element 15 among the plurality of dummy patterns 16a provided in the first insulating layer is shown in FIG. Is shown schematically. In the figure, the eddy current at each position in the dummy pattern 16P is indicated by an arrow, and the direction and magnitude of the eddy current are indicated by the direction and magnitude of the arrow, respectively. As shown in FIG. 4, although eddy current is generated near the base of the projection Ap of the dummy pattern 16P, compared with the magnitude of eddy current generated near the edge of the rectangular dummy pattern, Since the area occupied by the dummy pattern near the center of the outer dimensions of the dummy pattern 16P is small, it is relatively small and does not have a large influence on the whole. In addition, in the plurality of protrusions Ap located near the outer periphery of the outer dimensions, eddy currents are generated along the edges on both sides sandwiching the tips of the protrusions, but they are offset because the directions are opposite to each other. It is canceled out and does not become a large eddy current.

Next, an example of a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. FIG. 5 is a flowchart showing an outline of an example of the manufacturing process of the semiconductor device of the present invention. 6 is an enlarged cross-sectional view of the main part at the position indicated by the line AA in FIG. 1 of the sample corresponding to (a) to (f) of FIG. 5 in the first half in an example of the semiconductor device manufacturing process of the present invention. It is. Similarly, FIG. 7 shows an enlarged view of the main part at the position indicated by the line AA in FIG. 1 of the sample corresponding to (g) to (m) in FIG. It is sectional drawing. FIG. 8 is a plan view of a sample corresponding to FIG. 5E in the example of the manufacturing process. FIG. 9 is a view showing a sample corresponding to FIG. 5 (f) in an example of the manufacturing process, FIG. 9 (A) is a plan view, and FIG. 9 (B) is a view corresponding to FIG. It is a longitudinal cross-sectional view in the position shown by the -B line.
Similarly, FIG. 10 is a diagram showing a sample corresponding to (l) of FIG. 5 in an example of the manufacturing process, FIG. 10 (A) is a plan view, and FIG. 10 (B) is FIG. It is a longitudinal cross-sectional view in the position shown by a BB line.

First, as shown in FIGS. 5A and 6A, a first interlayer insulating film 12 a is formed on one main surface of the substrate 11. Next, as shown in FIGS. 5B and 6B, a first insulating layer 13a is formed on the first interlayer insulating film 12a. Next, as shown in FIGS. 5C and 6C, a plurality of grooves Tr are formed in the first insulating layer 13a at predetermined intervals. Next, as shown in FIGS. 5D and 6D, a plating underlayer is formed by sputtering on the first insulating layer 13a in which the plurality of grooves Tr are formed, and then a Cu plating layer is formed. Form. Next, as shown in FIGS. 5E, 6E, and 8, planarization is performed by CMP to obtain a plurality of dummy patterns 16a arranged at predetermined intervals. The series of steps (b) to (e) is called a so-called damascene technique.

Next, a second interlayer insulating film 12b is formed in the same manner as in FIG. Next, the second insulating layer 13b was formed using the damascene technique in the same manner as in the above (b) to (e), the trench Tr was formed in the second insulating layer 13b, and the Cu plating layer was formed. Thereafter, as shown in FIGS. 5 (f), 6 (f), 9 (A), and 9 (B), it is flattened by CMP to form a spiral lower layer wiring 15a of the inductance element 15, and the lower layer wiring 15a. And a plurality of dummy patterns 16b arranged at predetermined intervals.

Next, as shown in FIGS. 5G and 7G, a third interlayer insulating film 12c is formed. Next, as shown in FIGS. 5H and 7H, a hole H for forming a via connection portion is formed in the third interlayer insulating film 12c. Next, as shown in FIGS. 5I and 7I, a third insulating layer 13c is formed on the third interlayer insulating film 12c. Next, as shown in FIGS. 5J and 7J, a trench Tr is formed in the third insulating layer 13c. Next, as shown in FIGS. 5K and 7K, a Cu plating layer is formed. Next, it is planarized by CMP, and as shown in FIGS. 5 (l), 7 (l) and 10 (A), (B), the via connection portion 15b of the inductance element 15 and the spiral upper layer wiring 15c. Then, the lead-out upper layer wiring 15d and a plurality of dummy patterns 16c arranged at predetermined intervals around the upper layer wirings 15c and 15d are obtained.
The series of steps (g) to (l) is called a so-called dual damascene method.

Next, as shown in FIGS. 5 (m) and 7 (m), a protective layer 14 is formed. Next, as shown in FIG. 5 (n), after the terminal electrode 17 is formed by Cu selective plating, a plating layer 18 is formed on the surface of the terminal electrode 17 as necessary as shown in FIG. 5 (o). The semiconductor device 10 shown in FIGS. 1 to 3 is obtained.

Next, a preferred embodiment of the present invention will be described. First, a preferred embodiment of the substrate 11 is as follows. That As the substrate 11, a silicon substrate formed with SiO ₂ film on the surface by thermal oxidation of SiO _2, quartz substrate, and a sapphire substrate is preferable.

Next, preferred embodiments of the interlayer insulating films 12a, 12b, and 12c are as follows. That the interlayer insulating film 12a, 12b, as is 12c, for example Benzo Cyclo Butene (hereinafter referred to as BCB) or a photosensitive organic insulating material such as, preferably made of an inorganic insulating material such as SiO _2. The thickness of the interlayer insulating film 12 is preferably 2 to 20 μm, for example. In the case of an organic insulating material, the interlayer insulating films 12a, 12b, and 12c are preferably formed by applying, for example, a spin coating method and then curing by exposure and curing. In the case of an inorganic insulating material, it is preferably formed by chemical vapor deposition (hereinafter referred to as CVD method) or the like.

Next, preferred embodiments of the insulating layers 13a, 13b, and 13c are as follows. That is, the insulating layers 13a, 13b, and 13c are preferably made of a photosensitive organic insulating material such as BCB and an inorganic insulating material such as SiO _{2 in the same} manner as the interlayer insulating film. The thickness of the insulating layers 13a, 13b, 13c is preferably 2 to 20 μm, for example. In addition, in the case of the organic insulating material, the insulating layers 13a, 13b, 13c and the grooves in the insulating layers 13a, 13b, 13c are formed by applying unnecessary portions with a mask aligner, a stepper, etc. Preferably, it is selectively exposed, removed by development, and cured. In the case of an inorganic insulating material, it is preferable to form the film by a CVD method and selectively etch it.

Next, a preferred embodiment of the protective layer 14 is as follows. That is, the protective layer 14 is preferably made of BCB or SiO ₂ / SiN, like the interlayer insulating film. Moreover, it is preferable that the thickness of this protective layer 14 is 2-5 micrometers, for example. For example, in the case of BCB, the protective layer 14 may be formed by applying the spin coat method or the like, and then selectively exposing unnecessary portions with a mask aligner, a stepper, etc., removing by development, and curing. preferable. In the case of SiO2 / SiN, it is preferable to form the film by a CVD method and selectively etch it.

Next, a preferred embodiment of the inductance element 15 is as follows. That is, it is preferable that the inductance element 15 includes a spiral wiring. In the present embodiment, the spiral lower layer wiring 15a and the spiral upper layer wiring 15c have two layers of spiral wiring, but the present invention is not limited to this. For example, The spiral wiring may be only one layer, or may be three or more layers. Further, it is preferable to have a via connection portion for connecting a plurality of spiral wiring layers to each other or for pulling out an end portion on the inner peripheral side of the spiral wiring layer.
The inductance element 15 preferably has a wiring made of Cu. In addition, it is preferable to use a so-called damascene method for forming the wiring made of Cu. In this damascene method, an insulating layer having a groove is formed in advance, and the Cu layer is formed on the insulating layer by plating, sputtering, or the like, and then flattened by CMP, and the remainder of the Cu layer is wired or described later. It is used as a dummy pattern. In order to form the via connection portion simultaneously with the wiring, it is preferable to use a so-called dual damascene method. In the dual damascene method, a hole for providing a via is formed in an interlayer insulating film, an insulating layer having a groove is further formed on the interlayer insulating film in the same manner as the damascene method, and a metal layer is formed on the insulating layer. Then, the remaining portion of the metal layer in the hole is used as a via connection portion, and the remaining portion of the metal layer in the groove is used as a wiring or a dummy pattern to be described later. In order to form the metal layer by, for example, a plating layer, it is preferable to form a base layer in advance by sputtering, for example. The underlayer is preferably formed by sputtering, for example, with Ti of 10 nm and Cu of 100 nm, or TaN of 20 nm, Ta of 30 nm, and Cu of 100 nm. The present invention is not limited to a specific shape of a spiral inductance element, but can be applied to various sizes and various spiral inductance elements.

Next, a preferred embodiment of the terminal electrode 17 is as follows. That is, the terminal electrode 17 is preferably Cu, and the terminal electrode 17 is preferably formed by selective plating of Cu. Further, for example, a 4 μm thick Ni film and a 0.1 μm thick Au film are preferably sequentially formed on the surface of the terminal electrode by electroless plating.

Next, preferred embodiments of the dummy patterns 16, 16a, 16b, and 16c are as follows. That is, it is preferable that the dummy patterns 16, 16a, 16b, and 16c are made of Cu similarly to the wiring layer of the spiral inductance element 15. The dummy patterns 16, 16 a, 16 b, and 16 c are preferably formed by a damascene technique, similarly to the wiring layer of the spiral inductance element 15. In the case where the wiring is formed in the same layer as the wiring, it is preferably formed at the same time as the wiring.
The shape of the dummy pattern is preferably a polygonal shape having a plurality of protrusions with sharp edges at the tip. The number of the protrusions is preferably 3 or more, and more preferably. Further, when the number of the protrusions is as small as 3 to 7, the protrusion dimension of the protrusion may be larger than the remaining dimension obtained by subtracting the protrusion dimension of the protrusion from the outer dimension of the dummy pattern. preferable. Even when the number of the protrusions is large, it is preferable that the protrusion dimension of the protrusion is as large as possible with respect to the dimension of the remaining portion.
Moreover, in the said embodiment, although the dimension of several protrusion formed in a dummy pattern was equal, this invention is not limited to this, For example, some protrusions in several protrusion The tip angle, protrusion size, etc. may be different from those of other protrusions. Moreover, in the said embodiment, although the dimension and shape of the several dummy pattern arrange | positioned in the same layer were the same, this invention is not limited to this.
Moreover, it is preferable that the space | interval of the said several dummy pattern is comparable as the external dimension of the said dummy pattern, for example.
Further, in the above embodiment, the dimensions, shapes, and intervals of the plurality of dummy patterns arranged in each layer are equal to each other. However, the present invention is not limited to this, and for example, a dummy pattern is provided for each layer. The pattern dimensions, shapes, and intervals may be different.

(Example)
Next, an embodiment of the present invention will be described with reference to FIGS. The semiconductor device of this example is the same as the semiconductor device of the first embodiment.

First, as shown in FIGS. 5A and 6A, a silicon substrate 11 having a SiO ₂ layer formed on the surface by thermal oxidation is prepared, and a spin coating method is applied to one main surface of the substrate 11. Then, a BCB solution was applied to a thickness of 10 μm and exposed to form a first interlayer insulating film 12a. Next, as shown in FIGS. 5B and 6B, a BCB solution is applied to the thickness of 2 μm by spin coating on the first interlayer insulating film 12a, and selectively exposed with a mask aligner. Then, as shown in FIGS. 5C and 6C, a first insulating layer 13a having a plurality of trenches Tr was formed at a predetermined interval. Next, as shown in FIGS. 5D and 6D, a 10 nm-thick Ti underlayer and a thickness are formed by sputtering on the first insulating layer 13a in which the plurality of trenches Tr are formed. After sequentially forming a Cu underlayer of 100 nm, a Cu plating layer was formed by electrolytic plating. Next, as shown in FIGS. 5 (e), 6 (e) and 8, planarization was performed by CMP to obtain a plurality of dummy patterns 16a arranged at intervals of 30 μm. The dummy pattern 16 is a shape having a total of eight protrusions with a sharp tip at the tip, with an isosceles triangle having a base of 5 μm and a height of 9 μm coupled to each side of a regular octagon with a side of 5 μm. The thickness was 30 μm.

Next, in the same manner as in FIG. 5A, a second interlayer insulating film 12b made of BCB and having a thickness of 10 μm was formed. Next, a second insulating layer 13b made of BCB and having a thickness of 2 μm is formed by using the damascene technique in the same manner as in the above (b) to (e), and a plurality of grooves Tr Formed. Next, after forming a Cu plating layer in the same manner as described above, as shown in FIG. 5 (f), FIG. 6 (f), FIG. A spiral lower layer wiring 15a of the element 15 and a plurality of dummy patterns 16b arranged around the lower layer wiring 15a at intervals of 30 μm were obtained.

Next, as shown in FIGS. 5G and 7G, a third interlayer insulating film 12c made of BCB and having a thickness of 10 μm is formed in the same manner as described above, and FIGS. As shown in FIG. 7 (h), two holes H were formed in the third interlayer insulating film 12c for forming via connection portions. Next, as shown in FIG. 5 (i) and FIG. 7 (i), a BCB solution is applied onto the third interlayer insulating film 12c by spin coating, and selectively exposed by a mask aligner. As shown in FIG. 5J and FIG. 7J, the third insulating layer 13c having the two holes H and the plurality of grooves Tr was formed. Next, as shown in FIGS. 5 (k) and 7 (k), a Cu plating layer is formed in the same manner as described above, and then planarized by CMP to obtain FIGS. 5 (l) and 7 (l). 10A and 10B, the via connection portion 15b of the inductance element 15, the spiral upper layer wiring 15c, the leading upper layer wiring 15d, and the periphery of the upper layer wirings 15c and 15d are spaced by 30 μm. Thus, a plurality of dummy patterns 16c are obtained.

Next, as shown in FIG. 5 (m) and FIG. 7 (m), a BCB solution is applied by spin coating, and selectively exposed with a mask aligner to provide an opening at a location where a terminal electrode is to be formed. A protective layer 14 was formed. Next, after forming the terminal electrode 17 by Cu selective plating as shown in FIG. 5 (n), a plating layer 18 is formed on the surface of the terminal electrode 17 as shown in FIG. 1 to 3 were obtained. The wiring length of the inductance element 15 in the semiconductor device 10 was 1250 μm, and the wiring width was 20 μm.
(Comparative Example 1)
A semiconductor device of Comparative Example 1 was obtained in the same manner as in the previous example except that no dummy pattern was provided.
(Comparative Example 2)
A semiconductor device 110 of Comparative Example 2 shown in a plan view in FIG. 11 was obtained in the same manner as in the above example except that the shape of the dummy pattern 116 in plan view was a regular square of 30 μm □.
With respect to the semiconductor devices of Comparative Examples 1 and 2 and Examples obtained above, the results of measuring the no-load Q value at 0.1 MHz to 20 GHz of the inductance element formed in the semiconductor device are shown in FIG.
As is apparent from FIG. 12, the Q value in the vicinity of 7-8 GHz of the inductance element of the semiconductor layer device of Comparative Example 1 having no dummy pattern is 25, whereas a plurality of dummy patterns of 30 μm □ are provided. The Q value of the inductance element of the semiconductor device of Comparative Example 2 is greatly reduced to 21. Compared to this, the Q value in the vicinity of 7 to 8 GHz of the inductance element of the semiconductor device of the example of the present invention is approximately the same as the Q value of the inductance element of the semiconductor element of Comparative Example 1 that does not have a dummy pattern. Thus, it is understood that the deterioration of the Q value due to the generation of eddy current is suppressed.

  According to the present invention, it is possible to perform stable production by suppressing the occurrence of dishing and wiring pattern peeling, and it is suitable for various electronic devices using a semiconductor device in which the Q value of an inductance element is suppressed.

It is a top view which shows the outline | summary of 1st Embodiment of the semiconductor device of this invention. It is a longitudinal cross-sectional view in the AA line of FIG. 1 which shows the internal structure of the semiconductor device of the said 1st Embodiment. It is a longitudinal cross-sectional view in the BB line of FIG. 1 which shows the internal structure of the semiconductor device of the said 1st Embodiment. It is a figure which shows the electric current distribution inside the dummy pattern used for the semiconductor device of the said 1st Embodiment. 3 is a flowchart showing an example of a manufacturing process of a semiconductor device of the present invention. It is a longitudinal cross-sectional view in the position corresponding to the AA line of FIG. 1 for demonstrating later the process about the first half part of an example of the manufacturing process of the semiconductor device of this invention. It is a longitudinal cross-sectional view in the position equivalent to the AA line of FIG. 1 for demonstrating later the process about the latter half part of an example of the manufacturing process of the semiconductor device of this invention. It is a figure which shows an example of the manufacturing process of the semiconductor device of this invention. It is a figure which shows an example of the manufacturing process of the semiconductor device of this invention. It is a figure which shows an example of the manufacturing process of the semiconductor device of this invention. It is a top view which shows the semiconductor device of background art. It is a figure which shows the measurement result of the electrical property of the semiconductor device of this invention. It is a top view which shows the semiconductor device of background art.

Explanation of symbols

10: Semiconductor device 11: Substrates 12a, 12b, 12c: Interlayer insulating films 13a, 13b, 13c: Insulating layer 14: Protective layer 15: Inductive element 15a: Lower layer wiring 15b: Via connection portion 15c, 15d: Upper layer wiring 16: Dummy Pattern 16a: Dummy pattern 16b: Dummy pattern 16c: Dummy pattern 16P: Dummy pattern 17: Terminal electrode 18: Plating layer Ap: Projection with acute tip H: Hole Tr: Groove

Claims (2)

In a semiconductor device having a substrate, a dummy pattern formed on the substrate for controlling a chemical mechanical polishing process, and an inductance element formed in a spiral shape on the substrate,
2. The semiconductor device according to claim 1, wherein the dummy pattern has a polygonal shape having a plurality of protrusions with sharp edges. 2. The semiconductor device according to claim 1, wherein a plurality of the dummy patterns are arranged at a predetermined interval.

Images