RU2419145C1 - Analogue voltage multiplier - Google Patents

Abstract

FIELD: electricity. ^ SUBSTANCE: analogue voltage multiplier includes the first (1) (ux) and the second (2) opposite phase sources of input voltage of channel "X", the first (3) (uy3) and the second (4) (uy4) sources of input voltage of channel "Y", the first (5) and the second (6) input transistors the emitters of which are combined and connected to the first (7) current-stabilising bipole connected through the second output to the first (8) supply voltage source, the third (9) and the fourth (10) input transistors the emitters of which are combined and connected to the second (11) current-stabilising bipole connected through the second output to the first (8) power source, load circuit (12) connected to the second (13) power source, as well as the first (14) and the second (15) outputs of the device. At that, bases of the second (6) and the third (9) input transistors are combined, base of the first (5) input transistor is connected to the first (1) (ux) source of input voltage of channel "X"; collector of the first (5) input transistor is connected to the first (14) output of the device, collector of the fourth (10) input transistor is connected to the second (15) output of the device. To the circuit there introduced is the fifth (16), the sixth (17), the seventh (18) and the eighth (19) input transistors, emitters of the fifth (16) and the sixth (17) input transistors through the third (20) current-stabilising bipole are connected to the first (8) power source, emitters of the seventh (18) and the eighth (19) input transistors through the fourth (21) current-stabilising bipole are connected to the first (8) power source, bases of the second (6) and the third (9) input transistors are connected to the first (3) input voltage source (uy3) of channel "Y", bases of the sixth (17) and the seventh (18) input transistors are combined and connected to the second (4) input voltage source (uy4) of channel "Y", base of the fifth (16) input transistor is connected to base of the first (5) input transistor, base of the eighth (19) input transistor is connected to base of the fourth (10) input transistor and the second (2) input voltage source of channel "X", collectors of the second (6), the third (9), the sixth (17) and the seventh (18) input transistors are connected to output of additional voltage source (22), collector of the fifth (16) input transistor is connected to the second (18) output of the device, collector of the eighth (19) input transistor is connected to the first (14) output of the device. ^ EFFECT: decreasing supply voltage. ^ 7 cl, 17 dwg

Description

The present invention relates to the field of radio engineering and communication and can be used in automatic gain control devices, phase detectors and modulators, as well as in phase locked loop and frequency multiplication systems or as an amplifier, the voltage transfer coefficient of which depends on the level of the control signal.

The analog multiplier is the basic unit of modern systems for receiving and processing signals of the HF and microwave ranges of analog computing and measuring equipment, it allows us to solve the problems of allocating the difference frequency, attenuation of signals. APN is an integral part of quadrature modulators and demodulators, as well as synchronous filters. High-linear broadband APN can serve as a base cell of nonlinear SF blocks of systems on a chip.

The analog voltage multiplier (APN) of modern communication and telecommunication systems is implemented mainly on the basis of the Gilbert cell multiplier, which has been improved in more than 50 patents of leading microelectronic companies (see, for example, [1-16]).

On the basis of the Gilbert cell, not only voltage multipliers are realized, but also controlled amplifiers, and mixers (mixers) of the RF and microwave ranges, frequency doublers. In this sense, the APN is the basic functional unit of modern microelectronics, which determines the quality indicators of many communication systems.

The present invention relates to this class of devices.

противофазные источники входного напряжения канала «X», первый 3 (u_y3) и второй 4 (u_y4) источники входного напряжения канала «Y», первый 5 и второй 6 входные транзисторы, эмиттеры которых объединены и подключены к первому 7 токостабилизирующему двухполюснику, связанному вторым выводом с первым 8 источником напряжения питания, третий 9 и четвертый 10 входные транзисторы, эмиттеры которых объединены и подключены ко второму 11 токостабилизирующему двухполюснику, связанному вторым выводом с первым (8) источником питания, цепь нагрузки 12, связанную со вторым 13 источником питания, а также первым 14 и вторым 15 выходами устройства, причем базы второго 6 и третьего 9 входных транзисторов объединены, база первого 5 входного транзистора соединена с первым 1 (u_x) источником входного напряжения канала «X», коллектор первого 5 входного транзистора соединен с первым 14 выходом устройства, коллектор четвертого 10 входного транзистора соединен со вторым 15 выходом устройства.The closest prototype of the claimed device is an analog multiplier presented in the patent of Texas Instruments Inc. US No. 7024448 fig.2 containing the first 1 (u _x ) and second 2

antiphase sources of input voltage of the channel “X”, the first 3 (u _y3 ) and second 4 (u _y4 ) sources of the input voltage of the channel “Y”, the first 5 and second 6 input transistors, the emitters of which are combined and connected to the first 7 current-stabilizing bipolar connected the second terminal with the first 8 power supply source, the third 9 and fourth 10 input transistors, the emitters of which are combined and connected to the second 11 current-stabilizing two-terminal network connected by the second terminal to the first (8) power source, the load circuit 12, connected with the second 13 power supply, as well as the first 14 and second 15 outputs of the device, and the bases of the second 6 and third 9 input transistors are combined, the base of the first 5 input transistor is connected to the first 1 (u _x ) channel voltage input source “X”, the collector of the first 5 the input transistor is connected to the first 14 output of the device, the collector of the fourth 10 input transistor is connected to the second 15 output of the device.

A significant drawback of the known voltage multiplier is that it is inoperative at low supply voltages (for example, ± 1 V). This is due to the "two-tier" architecture of the APN prototype.

The main objective of the invention is to reduce the supply voltage to ± 0.9 · 1 B.

The first additional goal is to expand the frequency range by excluding from the structure of the APN controlled channel current sources "Y", which are implemented in the known scheme with four transistors. Such a number of inertial active elements affects the frequency range of the APN.

The second additional goal is to “bind” the input voltage sources u _x and u _y to the common bus of the power source. The solution to this problem greatly simplifies the coordination of the APN at the inputs with the signal sources u _x and u _y , which can be supplied relative to the common bus without static mode bias circuits that affect the stability of the zero level of the ARP.

противофазные источники входного напряжения канала «X», первый 3 (u_y3) и второй 4 (u_y4) источники входного напряжения канала «Y», первый 5 и второй 6 входные транзисторы, эмиттеры которых объединены и подключены к первому 7 токостабилизирующему двухполюснику, связанному вторым выводом с первым 8 источником напряжения питания, третий 9 и четвертый 10 входные транзисторы, эмиттеры которых объединены и подключены ко второму 11 токостабилизирующему двухполюснику, связанному вторым выводом с первым (8) источником питания, цепь нагрузки 12, связанную со вторым 13 источником питания, а также первым 14 и вторым 15 выходами устройства, причем базы второго 6 и третьего 9 входных транзисторов объединены, база первого 5 входного транзистора соединена с первым 1 (u_x) источником входного напряжения канала «X», коллектор первого 5 входного транзистора соединен с первым 14 выходом устройства, коллектор четвертого 10 входного транзистора соединен со вторым 15 выходом устройства, предусмотрены новые элементы и связи - в схему введены пятый 16, шестой 17, седьмой 18 и восьмой 19 входные транзисторы, эмиттер пятого 16 и шестого 17 входных транзисторов через третий 20 токостабилизирующий двухполюсник связаны с первым 8 источником питания, эмиттеры седьмого 18 и восьмого 19 входных транзисторов через четвертый 21 токостабилизирующий двухполюсник соединены с первым 8 источником питания, базы второго 6 и третьего 9 входных транзисторов подключены к первому 3 источнику входного напряжения (u_y3) канала «Y», базы шестого 17 и седьмого 18 входных транзисторов объединены и подключены ко второму 4 источнику входного напряжения (u_y4) канала «Y», база пятого 16 входного транзистора подключена к базе первого 5 входного транзистора, база восьмого 19 входного транзистора соединена с базой четвертого 10 входного транзистора и вторым 2

источником входного напряжения канала «X», коллекторы второго 6, третьего 9, шестого 17 и седьмого 18 входных транзисторов подключены к выходу дополнительного источника напряжения 22, коллектор пятого 16 входного транзистора соединен со вторым 18 выходом устройства, коллектор восьмого 19 входного транзистора связан с первым 14 выходом устройства.The goals are achieved in that in the ALP of figure 2, containing the first 1 (u _x ) and second 2

antiphase sources of input voltage of the channel “X”, the first 3 (u _y3 ) and second 4 (u _y4 ) sources of the input voltage of the channel “Y”, the first 5 and second 6 input transistors, the emitters of which are combined and connected to the first 7 current-stabilizing bipolar connected the second terminal with the first 8 power supply source, the third 9 and fourth 10 input transistors, the emitters of which are combined and connected to the second 11 current-stabilizing two-terminal network connected by the second terminal to the first (8) power source, the load circuit 12, connected with the second 13 power supply, as well as the first 14 and second 15 outputs of the device, and the bases of the second 6 and third 9 input transistors are combined, the base of the first 5 input transistor is connected to the first 1 (u _x ) channel voltage input source “X”, the collector of the first 5 the input transistor is connected to the first 14 output of the device, the collector of the fourth 10 input transistor is connected to the second 15 output of the device, new elements and communications are provided - the fifth 16, sixth 17, seventh 18 and eighth 19 input transistors are introduced into the circuit, the emitter is fifth 1 6 and the sixth 17 input transistors through the third 20 current-stabilizing bipolar connected to the first 8 power supply, the emitters of the seventh 18 and eighth 19 input transistors through the fourth 21 current-stabilizing bipolar connected to the first 8 power source, the base of the second 6 and third 9 input transistors are connected to the first 3 a source of input voltage (u _y3) channel «Y», the base 17 of the sixth and seventh input transistors 18 are combined and connected to the second input voltage source 4 (u _y4) channel «Y», base 16, fifth inlet tra ican connected to the base of the first input transistor 5, the base 19 of the eighth input transistor connected to the base of the fourth transistor 10 and second input 2

the source of the input voltage of the channel "X", the collectors of the second 6, third 9, sixth 17 and seventh 18 input transistors are connected to the output of the additional voltage source 22, the collector of the fifth 16 input transistor is connected to the second 18 output of the device, the collector of the eighth 19 input transistor is connected to the first 14 device output.

In Fig.1 shows a diagram of the APN prototype, and Fig.2 is a diagram of the claimed APN in accordance with claim 1, claim 2, claim 3 and claim 4 of the claims.

Figure 3 shows graphs explaining the features of the APN of figure 2 - the dependence of the gain K _{at the} upper (input transistors 5, 6, 9, 10) and lower (input transistors 16, 17, 18, 19) gain channels on the ratio of the areas emitter junction input transistors

и

,

and

,

where SK.n is the area of the emitter junctions of the k-th and n-th transistors.

When N _in = N _n = 16, the initial position of the operating point (u _y = 0) corresponds to the coordinate Q.

Figure 4 shows the diagram of the APN in accordance with paragraph 4 of the claims.

Figure 5 shows the diagram of the APN in accordance with paragraph 5 and paragraph 6 of the claims

.Figure 6 shows graphs explaining the features of the operation of the ALS of figure 5 - the dependence of the transmission coefficient of voltage K _{at the} upper (5, 6, 9, 10) and lower (16, 17, 18, 19) gain channels with a zero offset of their characteristics control K _y = f (u _y ) by

.

первого 3 и второго 4 источников входного напряжения канала «Y» имеют одинаковую полярность и создаются за счет делителей напряжения на резисторах 30, 31 и 33, 34.In Fig.7 shows a diagram of the APN corresponding to Fig.5, in which the constant components

the first 3 and second 4 sources of input voltage of the channel "Y" have the same polarity and are created by voltage dividers on resistors 30, 31 and 33, 34.

On Fig shows a diagram of the APN in accordance with paragraph 7 of the claims.

и

- для верхнего и нижнего каналов усиления при синфазном изменении переменных составляющих e_y (27) и e_y (28).Fig. 9 is a graph explaining the features of the operation of the ALP of Fig. 8 - when the control characteristics K _y = f (u _y ) are shifted by zero

and

- for the upper and lower gain channels with the in-phase change of the variable components e _y (27) and e _y (28).

и второго

источников входного напряжения канала «Y» имеют противоположную полярность и создаются за счет применения резистивных делителей напряжения на элементах 30, 31 и 33, 34.Figure 10 shows a diagram of the APN corresponding to figure 8, in which the constant components of the first

and second

Channel “Y” input voltage sources have opposite polarity and are created by using resistive voltage dividers on elements 30, 31 and 33, 34.

In Fig.11 - Fig.12 shows the diagram of the APN of Fig.4 and its static mode in the Cadance computer simulation environment, and the drawing of Fig.13 shows the dependence of the module of its voltage gain K _u = u _out / u _x on the control voltage level u _y = U _var . Such a measurement mode K _u characterizes the use of the claimed APN as a controlled amplifier.

In Fig.14 shows the results of computer simulation of the circuit of Fig.11 for the case of the multiplication of two voltages u _x and u _y . These graphs show that the claimed APN is a four-quadrant multiplier.

On Fig shows the dependence of the output voltage of the APN of Fig.11 when working with signals u _x = 1 mV, f _x = 1 GHz and u _y = 1 mV, f _y = 10 MHz.

The output voltage spectra of the APN of FIG. 11 corresponding to FIG. 15 are shown in FIG. 16 and FIG. 17 at different scales along the frequency axis.

противофазные источники входного напряжения канала «X», первый 3 (u_y3) и второй 4 (u_y4) источники входного напряжения канала «Y», первый 5 и второй 6 входные транзисторы, эмиттеры которых объединены и подключены к первому 7 токостабилизирующему двухполюснику, связанному вторым выводом с первым 8 источником напряжения питания, третий 9 и четвертый 10 входные транзисторы, эмиттеры которых объединены и подключены ко второму 11 токостабилизирующему двухполюснику, связанному вторым выводом с первым (8) источником питания, цепь нагрузки 12, связанную со вторым 13 источником питания, а также первым 14 и вторым 15 выходами устройства, причем базы второго 6 и третьего 9 входных транзисторов объединены, база первого 5 входного транзистора соединена с первым 1 (u_x) источником входного напряжения канала «X», коллектор первого 5 входного транзистора соединен с первым 14 выходом устройства, коллектор четвертого 10 входного транзистора соединен со вторым 15 выходом устройства. В схему введены пятый 16, шестой 17, седьмой 18 и восьмой 19 входные транзисторы, эмиттер пятого 16 и шестого 17 входных транзисторов через третий 20 токостабилизирующий двухполюсник связаны с первым 8 источником питания, эмиттеры седьмого 18 и восьмого 19 входных транзисторов через четвертый 21 токостабилизирующий двухполюсник соединены с первым 8 источником питания, базы второго 6 и третьего 9 входных транзисторов подключены к первому 3 источнику входного напряжения (u_y3) канала «Y», базы шестого 17 и седьмого 18 входных транзисторов объединены и подключены ко второму 4 источнику входного напряжения (u_y4) канала «Y», база пятого 16 входного транзистора подключена к базе первого 5 входного транзистора, база восьмого 19 входного транзистора соединена с базой четвертого 10 входного транзистора и вторым 2

источником входного напряжения канала «X», коллекторы второго 6, третьего 9, шестого 17 и седьмого 18 входных транзисторов подключены к выходу дополнительного источника напряжения 22, коллектор пятого 16 входного транзистора соединен со вторым 18 выходом устройства, коллектор восьмого 19 входного транзистора связан с первым 14 выходом устройства.The inventive ALP of figure 2 contains the first 1 (u _x ) and second 2

antiphase sources of input voltage of the channel “X”, the first 3 (u _y3 ) and second 4 (u _y4 ) sources of the input voltage of the channel “Y”, the first 5 and second 6 input transistors, the emitters of which are combined and connected to the first 7 current-stabilizing bipolar connected the second terminal with the first 8 power supply source, the third 9 and fourth 10 input transistors, the emitters of which are combined and connected to the second 11 current-stabilizing two-terminal network connected by the second terminal to the first (8) power source, the load circuit 12, connected with the second 13 power supply, as well as the first 14 and second 15 outputs of the device, and the bases of the second 6 and third 9 input transistors are combined, the base of the first 5 input transistor is connected to the first 1 (u _x ) channel voltage input source “X”, the collector of the first 5 the input transistor is connected to the first 14 output of the device, the collector of the fourth 10 input transistor is connected to the second 15 output of the device. The fifth 16th, sixth 17th, seventh 18th and eighth 19th input transistors are introduced into the circuit, the fifth 16th and sixth 17th input transistor emitters are connected through the third 20 current-stabilizing two-terminal devices to the first 8 power supply, the seventh 18th and eighth 19th transistor emitters through the fourth 21 current-stabilizing two-terminal devices 8 are connected to a first power source, bases of the second 6 and third 9 input transistors 3 are connected to first input voltage source (u _y3) channel «Y», the base 17 of the sixth and seventh transistors 18 combined input and Connectivity 4 yucheny second input voltage source (u _y4) channel «Y», the base of the fifth input transistor 16 is connected to the base 5 of the first input transistor, the base of the eighth input transistor 19 is connected to the base of the fourth transistor 10 and second input 2

the source of the input voltage of the channel "X", the collectors of the second 6, third 9, sixth 17 and seventh 18 input transistors are connected to the output of the additional voltage source 22, the collector of the fifth 16 input transistor is connected to the second 18 output of the device, the collector of the eighth 19 input transistor is connected to the first 14 device output.

, а первый 3 источник входного напряжения канала «Y»

противофазен второму 4 источнику входного напряжения канала «Y» (u_y4).In the circuit of FIG. 2, in accordance with claim 2, the areas of emitter pn junctions of the second 6, third 9, sixth 17 and seventh 18 input transistors are N times the areas of the emitter pn junctions of the first 5, fourth 10, fifth 16 and eighth 19 input transistors, and the first 1 source of input voltage of the channel "X" (u _x ) is out of phase with the second 2 source of input voltage of the channel "X"

, and the first 3 source voltage input channel "Y"

out of phase to the second 4 source of the input voltage of the channel "Y" (u _y4 ).

Moreover, in accordance with claim 3 of the invention, the areas of emitter pn junctions of the second 6, third 9, sixth 17 and seventh 18 input transistors are approximately 16 times larger than the areas of emitter pn junctions of the first 5, fourth 10, fifth 16 and eighth 19 input transistors (N ≈16).

In addition, in the circuit of FIG. 2 and FIG. 4, in accordance with claim 4, the voltage of the additional source 22 is approximately equal to the static voltage on the collectors of the first 5, third 10, fifth 16, and eighth 19 input transistors, and the load circuit is made in the form of resistors 23 and 24.

постоянную составляющую, а второй 4 источник входного напряжения канала «Y» имеет вторую 26 постоянную составляющую

.In the circuit of FIG. 5, in accordance with claim 5, the first 3 channel “Y” input voltage source has a first 25

a constant component, and the second 4 source voltage input channel "Y" has a second 26 constant component

.

и вторая 26

постоянные составляющие первого 3 и второго 4 источников входного напряжения канала «Y» приблизительно одинаковы по величине и имеют одинаковую полярность, а переменные составляющие первого 3 (27) и второго 4 (28) источников входного напряжения канала «Y» противофазны.In the diagram of FIG. 5, in accordance with claim 6, the first 25

and second 26

the constant components of the first 3 and second 4 sources of input voltage of the channel “Y” are approximately the same in magnitude and have the same polarity, and the alternating components of the first 3 (27) and second 4 (28) sources of input voltage of the channel “Y” are out of phase.

и вторая 26

постоянные составляющие первого 3 и второго 4 источников входного напряжения канала «Y» приблизительно одинаковы по величине, но имеют противоположную полярность, а переменные составляющие первого 3 (27) и второго 4 (28) источников входного напряжения канала «Y» синфазны.In the diagram of FIG. 8, in accordance with claim 7, the first 25

and second 26

the constant components of the first 3 and second 4 sources of input voltage of the channel “Y” are approximately the same in magnitude, but have opposite polarity, and the alternating components of the first 3 (27) and second 4 (28) sources of input voltage of the channel “Y” are in phase.

Consider the operation of the APN of figure 2.

The static current mode of the input transistors 5, 6, 9, 10 (upper gain channel) and 16, 17, 18 and 19 (lower gain channel) is set by current-stabilizing two-terminal devices 7, 11, 20 and 21. In a particular case, these two-terminal devices can be resistors . In APN circuits having voltages of the first 8 and second 13 power supplies of more than 1.5 ÷ 1.6 V, these transistor-based two-terminal circuits can use the classic transistor current stabilizers or current mirrors described in the technical literature.

The voltage at the outputs 14 and 15 of the APN of FIG. 2 depends on the currents flowing in the load resistors 23 and 24. In turn, alternating currents through these resistors are formed by input transistors 5, 6, 9, 10 (upper gain channel) and input transistors 16 , 17, 18, and 19 (lower gain channel). Moreover, these currents have several components:

- переменные токи, пропорциональные u_x, формируемые верхним каналом усиления на входных транзисторах 5, 6, 9, 10;

- alternating currents proportional to u _x formed by the upper gain channel at the input transistors 5, 6, 9, 10;

- переменные токи, пропорциональные u_x, формируемые нижним каналом усиления на входных транзисторах 16, 17, 18, 19;

- alternating currents proportional to u _x generated by the lower gain channel at the input transistors 16, 17, 18, 19;

- переменные токи, зависящие от сигнала управления u_y транзисторами верхнего канала усиления (элементы 5, 6, 9,10);

- alternating currents, depending on the control signal u _y transistors of the upper gain channel (elements 5, 6, 9,10);

- переменные токи, зависящие от сигнала управления u_y транзисторами нижнего канала усиления (элементы 16,17,18, 19).

- alternating currents, depending on the control signal u _y transistors of the lower gain channel (elements 16,17,18, 19).

,

,

,

определяются сопротивлениями эмиттерных переходов соответствующих транзисторов, которые управляются напряжениями u_y3 и u_y4. При этом увеличение положительного напряжения источника 3 входного напряжения канала «Y» u_y3 вызывает уменьшение коэффициентов передачи сигналов u_x(1) и

(2) со входов Вх.х₁ и Вх.х₂ канала «X» через входные транзисторы 5, 6, 9, 10 (верхний канал усиления) в цепь нагрузки (фиг.3), а увеличение отрицательного напряжения источника сигнала (4) u_y4 приводит к увеличению противофазной передачи u_x (1) и

(2) через транзисторы 16, 17, 18, 19 в цепь нагрузки (12) по нижнему каналу усиления (фиг.3б). Если u_y3=u_y4=0, то передача u_x и

на выход будет близка к нулю.Numerical values of currents

,

,

,

are determined by the resistance of the emitter junctions of the respective transistors, which are controlled by the voltages u _y3 and u _y4 . In this case, an increase in the positive voltage of the source 3 of the input voltage of the channel “Y” u _y3 causes a decrease in the transmission coefficients of the signals u _x (1) and

(2) from inputs Вх.х ₁ and Вх.х _{2 of the} channel “X” through the input transistors 5, 6, 9, 10 (upper gain channel) to the load circuit (Fig. 3), and the increase in the negative voltage of the signal source (4 ) u _y4 leads to an increase in antiphase transmission u _x (1) and

(2) through transistors 16, 17, 18, 19 to the load circuit (12) along the lower gain channel (Fig.3b). If u _y3 = u _y4 = 0, then the transmission u _x and

the exit will be close to zero.

These dependencies are confirmed by the graphs of Fig. 15, Fig. 14, which indicate that the inventive device of Fig. 2 is an analog multiplier of small signals u _x and u _y .

To expand the operating range of changes in u _x and u _y, one should use the preliminary logarithm of these signals, which is used in traditional schemes of multipliers based on a Gilbert cell.

The first significant feature of the claimed device is that the area of the emitter junctions of the input transistors 6, 9, 17 and 18 is N-times greater than the area of the emitter junctions of the input transistors 5.10, 16, 19. When N _in = N _n = 16 and u _y = 0, the transmission coefficients of the signals u _x and u _y to the load circuit through transistors 5, 6, 9, 10 (upper channel) and transistors 16, 17, 18, 19 (lower channel) are the same and are approximately half of the maximum value transmission coefficients K _y on these channels of figure 3. If N = N _{to n} ≠ 16, the transmission coefficients of the channel when u _y = 0 are not equal, which leads to nessimetrii control characteristics (Figure 6) and lower allowable stress amplitudes being multiplied. At N = 1, as well as at N >> 1, the circuit of FIG. 2 loses the properties of the voltage multiplier u _x and u _y . Thus, it should be emphasized that the optimal performance of the circuit of figure 2 is provided only in the case when N _in = N _n ≈16.

The second significant feature of the circuit of FIG. 2, which is mandatory for any multipliers, is that the transmission of voltage sources 3 and 4 u _y3 and u _y4 to the load circuit 12 is close to zero.

For summing points Σ ₁ and Σ ₂ in the diagram of figure 2, the conditions are satisfied:

Therefore, the control signal u _y = u _y3 = u _{y4 is} absent in the load 12, which is typical for voltage multipliers.

The spectrum of output signals when multiplying u _x and u _y with a frequency of 1 GHz and 10 MHz is shown in Fig. 14, Fig. 15, which shows that the first harmonics of the input signals f _x and f _{y are} practically absent in the output signal. This property is typical for voltage multipliers.

показывает, что при малых амплитудах выходного напряжения в АПН фиг.2

напряжения

. Отрицательное напряжение питания

при использовании известных способов стабилизации может принимать значение

. Таким образом, общее напряжение питания АПН фиг.2

, что недостижимо в АПН-прототипе.Minimum Supply Voltage Limit Analysis

shows that at small amplitudes of the output voltage in the APN of figure 2

voltage

. Negative supply voltage

when using known stabilization methods can take on value

. Thus, the total supply voltage of the APN of FIG. 2

that is unattainable in the APN prototype.

Thus, the proposed device performs the functions of a signal multiplier, can operate at low supply voltages, provides a wider range of operating frequencies and does not require input matching static mode circuits that adversely affect the stability of zero APN.

BIBLIOGRAPHIC LIST

1. Patent US 7024448 fig. 2.

2. Patent US 5157350 fig. 2.

3. Patent US 5877974 fig. 4.

4. Patent US 5886916 fig. 2.

5. Patent US 3689752.

6. Patent US 5684419 fig. 3.

7. Patent US 4458211.

8. Patent US 4572975.

9. Patent US 5889425.

10. Patent US 5331289 fig. 1.

11. Patent US 5914639 fig. 4.

12. Patent US 6111463 fig. 11.

13. Patent US 5886560 fig. 1.

14. Patent application US 2006/0232334 fig. 1.

15. Patent JP 53-25780, cl. 98 (5).

16. Patent EP 917285 fig. 1.

Claims (7)

1. An analog voltage multiplier containing the first (1) (u _x ) and second (2)

antiphase sources of input voltage of channel X, the first (3) (u _y3 ) and second (4) (u _y4 ) sources of input voltage of channel Y, first (5) and second (6) input transistors, the emitters of which are combined and connected to the first ( 7) a current-stabilizing two-terminal connected to the second output terminal with a first (8) power supply source, a third (9) and fourth (10) input transistors, the emitters of which are combined and connected to a second (11) current-stabilizing two-terminal device connected to the first terminal (8) power supply, load circuit (12), connected with the second (13) power source, as well as the first (14) and second (15) outputs of the device, the bases of the second (6) and third (9) input transistors combined, the base of the first (5) input transistor connected to the first (1 ) (u _x ) the input voltage channel X, the collector of the first (5) input transistor is connected to the first (14) output of the device, the collector of the fourth (10) input transistor is connected to the second (15) output of the device, characterized in that the circuit is introduced fifth (16), sixth (17), seventh (18) and eighth (19) input transistors, fifth emitter of the second (16) and sixth (17) input transistors are connected through the third (20) current-stabilizing two-terminal to the first (8) power source, the emitters of the seventh (18) and eighth (19) input transistors are connected to the first (fourth) current-stabilizing two-terminal 8) the power source, the base of the second (6) and third (9) input transistors are connected to the first (3) input voltage source (u _y3 ) of channel Y, the bases of the sixth (17) and seventh (18) input transistors are combined and connected to the second (4) the input voltage source (u _y4 ) of channel Y, the base of the fifth (16) the input transistor is connected to the base of the first (5) input transistor, the base of the eighth (19) input transistor is connected to the base of the fourth (10) input transistor and the second (2)

the input voltage channel X, the collectors of the second (6), third (9), sixth (17) and seventh (18) input transistors are connected to the output of an additional voltage source (22), the collector of the fifth (16) input transistor is connected to the second (18 ) by the device output, the collector of the eighth (19) input transistor is connected to the first (14) device output. 2. The analog voltage multiplier according to claim 1, characterized in that the area of the emitter pn junctions of the second (6), third (9), sixth (17) and seventh (18) input transistors is N times the area of the emitter pn junctions of the first ( 5), the fourth (10), fifth (16) and eighth (19) input transistors, the first (1) channel X input voltage source

out of phase with the second (2) channel X input voltage source

and the first (3) channel voltage input source Y (u _y1 ) is out of phase with the second (4) channel voltage input source Y (u _y2 ). 3. The analog voltage multiplier according to claim 1, characterized in that the area of the emitter pn junctions of the second (6), third (9), sixth (17) and seventh (18) input transistors is approximately 16 times the area of the emitter pn junctions of the first ( 5), the fourth (10), fifth (16) and eighth (19) input transistors (N≈16). 4. The analog voltage multiplier according to claim 1, characterized in that the voltage of the additional source (22) is approximately equal to the static voltage on the collectors of the first (5), third (10), fifth (16) and eighth (19) input transistors. 5. The analog voltage multiplier according to claim 1, characterized in that the first (3) channel Y input voltage source has a first (25) DC component, and the second (4) channel Y input voltage source has a second (26) DC component. 6. The analog voltage multiplier according to claim 5, characterized in that the first (25) and second (26) DC components of the first (3) and second (4) channel Y input voltage sources are approximately the same in magnitude and have the same polarity, and the variables the components of the first (3) (27) and second (4) (28) sources of the input voltage of channel Y are out of phase. 7. The analog voltage multiplier according to claim 5, characterized in that the first (25) and second (26) DC components of the first (3) and second (4) channel “Y” input voltage sources are approximately equal in magnitude but have opposite polarity , and the alternating components of the first (3) (27) and second (4) (28) sources of the input voltage of channel Y are in phase.

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