RU2353967C1 - Logical calculator - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: logical calculator is intended for implementation of n simple symmetric Boolean function depending on n arguments - input binary signals- and can be used in computer engineering digital systems as code conversion facility. The device contains n closing keys, n opening keys, n AND elements, n OR elements and n D-triggers.

EFFECT: device functionality enhancement due to implementation of parallel or sequential Boolean functions set depending on sequential or parallel set of specified arguments respectively.

2 dwg, 2 tbl

Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logic calculators are known (see, for example, Fig. 1 in the description of the invention to the patent of the Russian Federation 2276399, class G06F 7/00, 2006), which implement a parallel set of n simple symmetric Boolean functions depending on a sequential set of n arguments - input binary signals.

The reason that impedes the achievement of the technical result indicated below when using well-known logical computers is limited functionality due to the fact that the sequential set of n simple symmetric Boolean functions is not implemented, depending on the parallel set of n arguments - input binary signals.

The closest device of the same purpose to the claimed invention in terms of features is the logic calculator adopted as a prototype (Fig. 1 in the description of the invention to the patent of the Russian Federation 2282234, class G06F 7/57, 2006), which contains n locking, n disconnecting keys , n AND elements, n OR elements, n D-flip-flops and implements a sequential set of n simple symmetric Boolean functions depending on a parallel set of n arguments - input binary signals.

The reason that impedes the achievement of the technical result indicated below when using the prototype is limited functionality due to the fact that the parallel set of n simple symmetric Boolean functions is not implemented, depending on a sequential set of n arguments - input binary signals.

The technical result of the invention is the expansion of functionality by providing the implementation of a parallel set of n simple symmetric Boolean functions depending on a sequential set of n arguments - binary input signals or a sequential set of these functions depending on a parallel set of these arguments.

элемента И соединены соответственно с вторым и первым входами i-го элемента ИЛИ, выход i-го замыкающего и выход i-го размыкающего ключей объединены, а их вход управления соединен с первым управляющим входом логического вычислителя, подсоединенного вторым управляющим входом к тактовому входу i-го D-триггера, особенность заключается в том, что выход k-го

элемента И и выход i-го элемента ИЛИ подключены соответственно к первому входу (k+1)-го элемента И и входу данных i-го D-триггера, неинвертирующий выход которого соединен с входом i-го размыкающего ключа, подсоединенного выходом к первому входу i-го элемента ИЛИ, выход которого соединен с i-ым параллельным выходом логического вычислителя, подключенного i-ым параллельным входом, последовательным входом и последовательным выходом соответственно к входу i-го замыкающего ключа, первому входу первого и выходу n-го элементов И.The specified technical result in the implementation of the invention is achieved by the fact that in a logical computer containing n locking, n opening keys, n AND elements, n OR elements and n D-flip-flops, the first and second inputs of the i-th

AND elements are connected respectively to the second and first inputs of the i-th OR element, the output of the i-th closing and the output of the i-th disconnecting keys are combined, and their control input is connected to the first control input of the logic computer connected to the second control input by the i-input th D-flip-flop, the peculiarity is that the output of the kth

element AND and the output of the i-th element OR are connected respectively to the first input of the (k + 1) -th element And and the data input of the i-th D-flip-flop, the non-inverting output of which is connected to the input of the i-th disconnect key, connected by the output to the first input of the i-th OR element, the output of which is connected to the i-th parallel output of the logic computer connected by the i-th parallel input, serial input and serial output, respectively, to the input of the i-th closing key, the first input of the first and the output of the nth elements I.

Figure 1 and figure 2 presents, respectively, a diagram of the proposed logical computer and timing diagrams explaining the principle of its operation.

первый и второй входы элемента

соединены соответственно с первым входом элемента 3_k+1, вторым и первым входами элемента 4_i, выход которого подключен к входу данных D-триггера 5_i, подсоединенного неинвертирующим выходом к входу ключа 2_i, выход которого соединен с выходом ключа 1_i и первым входом элемента 4_i, подсоединенного выходом к i-му параллельному выходу логического вычислителя, i-й параллельный вход, последовательный вход, последовательный выход, первый и второй управляющие входы которого соединены соответственно с входом ключа 1_i, первым входом элемента 3_i, выходом элемента 3_n, входом управления ключей 1_i, 2_i и тактовым входом D-триггера 5_i.The logic computer contains n closing keys 1 ₁ , ..., 1 _n , n breaking keys 2 ₁ , ..., 2 _n , n elements AND 3 ₁ , ..., 3 _n , n elements OR 4 ₁ , ..., 4 _n and n D- triggers 5 ₁ , ..., 5 _n , and the output of the element

first and second inputs of an element

connected respectively to the first input of the element 3 _{k + 1} , the second and first inputs of the element 4 _i , the output of which is connected to the data input of the D-trigger 5 _i , connected by a non-inverting output to the input of the key 2 _i , the output of which is connected to the output of the key 1 _i and the first an input member 4 _i, connected to the output of i-th parallel output logic solver, i-th parallel input, a serial input, a serial output, the first and second control inputs of which are respectively connected to the input of the switch 1 _i, the first input member 3 _i, yield element 3 _n, keys control input 1 _i, 2 _i and a clock input of D-flip-flop 5 _i.

The work of the proposed logical computer is as follows. Pulse signals y ₁ , y ₂ ∈ {0,1} (figure 2) are respectively supplied to its first and second control inputs, and the duration T ^{* of the} high signal level at ₁ and the period T of the signal at ₂ must satisfy the conditions T ^* > Δt ^* and T> Δt, where

замкнут (разомкнут), а ключ 2_i разомкнут (замкнут). Тогда сигналы на выходах элементов 3_i, 4_i будут определяться рекуррентными выражениямиΔt ^* = nΔt _And , Δt = Δt _Tp + nΔt _And , a Δt _Tr and Δt _And are the durations of the delays introduced by the D-trigger and element I. The arguments of the functions being implemented are binary input signals x ₁ , ..., x _n ∈ {0, l} either are fed sequentially according to FIG. 2 to the serial input of the logic computer (in this case, the logical “0” is fixed at its first, ..., nth parallel inputs), or parallelly fed to the first, ..., nth parallel inputs of the logical the calculator (in this case, a logical “1” is fixed on its serial input). If y ₁ = 1 (y ₁ = 0), then the key

closed (open), and key 2 _i open (closed). Then the signals at the outputs of the elements 3 _i , 4 _i will be determined by recurrence expressions

есть номер момента времени t_j (фиг.2); V_i0=x_i, W_0j=1 либо V_i0=0, W_0j=x_j. В представленных ниже табл.1 и табл.2 приведены значения выражений (1) при n=4, если соответственно V_i0=х_i, W_0j=1 и V_i0=0, W_0j=x_j.Where

there is the number of time t _j (figure 2); V _i0 = x _i , W _0j = 1 or V _i0 = 0, W _0j = x _j . In the following table 1 and table 2, the values of expressions (1) are given for n = 4 if, respectively, V _i0 = x _i , W _0j = 1 and V _i0 = 0, W _0j = x _j .

Table 1 W ₁₁ = x ₁
V ₁₁ = 1

W ₂₁ = x ₁ x ₂

W ₃₁ = x ₁ x ₂ x ₃

W ₄₁ = x ₁ x ₂ x ₃ x ₄

W ₁₂ = 1
V ₁₂ = 1

V ₂₂ = 1

W ₁₃ = 1
V ₁₃ = 1 W ₂₃ = 1
V ₂₃ = 1

V ₃₃ = 1

W ₁₄ = 1
V ₁₄ = 1 W ₂₄ = 1
V ₂₄ = 1 W ₃₄ = 1
V ₃₄ = 1

V ₄₄ = 1

table 2 W ₁₁ = 0
V ₁₁ = x ₁

W ₁₂ = x ₁ x ₂

W ₂₁ = 0
V ₂₁ = 0 W ₂₂ = 0
V ₂₂ = x ₁ x ₂ W ₂₃ = x ₁ x ₂ x ₃

W ₃₁ = 0
V ₃₁ = 0 W ₃₂ = 0
V ₃₂ = 0 W ₃₃ = 0
V ₃₃ = x ₁ x ₂ x ₃ W ₃₄ = x ₁ x ₂ x ₃ x ₄

W ₄₁ = 0
V ₄₁ = 0 W ₄₂ = 0
V ₄₂ = 0 W ₄₃ = 0
V ₄₃ = 0 W ₄₄ = 0
V ₄₄ = x ₁ x ₂ x ₃ x ₄

Thus, with V _i0 = x _i and W _0j = 1 at the serial output of the proposed logical computer, we have

and with V _i0 = 0, W _0j = x _j and j = n at its first, second, ..., n-th parallel outputs, respectively, we have

where τ ₁ , ..., τ _n are simple symmetric Boolean functions (see page 126 in the book Pospelov D. A. Logical methods of analysis and synthesis of circuits. M .: Energy, 1974).

The above information allows us to conclude that the proposed logical computer has wider functionality compared to the prototype, as it provides a parallel set of n simple symmetric Boolean functions depending on a sequential set of n arguments - input binary signals, or a sequential set of these functions depending from a parallel set of specified arguments.

Claims (1)

A logic computer designed to implement n simple symmetric Boolean functions depending on n arguments - input binary signals, containing n closing, n opening keys, n AND elements, n OR elements and n D-triggers, with the first and second inputs of the ith

AND elements are connected respectively to the second and first inputs of the nth OR element, the output of the i-th closing and the output of the i-th disconnecting keys are combined, and their control input is connected to the first control input of the logic computer connected to the second control input by the clock input i- th D-trigger, characterized in that the output of the kth

element AND and the output of the i-th element OR are connected respectively to the first input of the (k + 1) -th element And and the data input of the i-th D-flip-flop, the non-inverting output of which is connected to the input of the i-th disconnect key, connected by the output to the first input of the i-th OR element, the output of which is connected to the i-th parallel output of the logic computer connected by the i-th parallel input, serial input and serial output, respectively, to the input of the i-th closing key, the first input of the first and the output of the nth elements I.

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