RU2319293C1 - Cascade differential amplifier - Google Patents

Abstract

FIELD: radio engineering and communications, possible use as device for amplification of analog signals, in structure of analog microchips of various functional purposes (for example, in operational amplifiers with low values of zero shift EMF).

SUBSTANCE: cascade differential amplifier contains input differential cascade (1), transistors (2) and (3) of intermediate cascade, bases of which are connected to shifting voltage supply (4), and emitters are connected to outputs (5) and (6) of differential cascade (1) and through first (7) and second (8) current-stabilizing dipoles are connected to bus of first (9) power supply, where collector of transistor (3) of intermediate cascade is connected to input (10) of buffer amplifier (11) and collector of transistor (12) of intermediate cascade, emitter of which is connected to emitter of transistor (13) of intermediate cascade and to bus of second intermediate cascade (14), and base is connected to base of transistor (13) and collector of transistor (2). An additional transistor (15) is introduced to the circuit, base of which is connected to common bus of first (9) and second (14) current supplies, collector is connected to emitter of transistor (2), and emitter is connected to collector of transistor (13), resulting in reduction of zero shift EMF of cascade differential amplifier due to identical shift of input characteristics of transistors (13) and (12), caused by influence of Early effect.

EFFECT: increased efficiency.

2 cl, 6 dwg

Description

The invention relates to the field of radio engineering and communication and can be used as a device for amplifying analog signals, in the structure of analog microcircuits of various functional purposes (for example, operational amplifiers with small values of the emf of zero bias (OA)).

Known circuits of the so-called “bent” cascode differential amplifiers (DU) on npn and pnp transistors [1-36], which became the basis of more than 20 serial operational amplifiers manufactured as foreign (HA2520, HA5190, AD797, AD8631, AD8632, OP90 and etc.), and Russian (154UDZ, etc.) microelectronic firms. Due to the high popularity of such a remote control architecture, more than 200 patents have been issued for their modification. The present invention relates to this subclass of devices.

The closest prototype (figure 1) of the claimed device is the cascode differential amplifier (CDA) described in US patent No. 6696888 containing the input differential stage 1, the first 2 and second 3 output transistors of the intermediate stage, the bases of which are connected to a bias voltage source 4, and emitters are connected to the outputs 5 and 6 of the input differential stage 1 and through the first 7 and second 8 current-stabilizing two-terminal circuits are connected to the bus of the first 9 power source, and the collector of the second output transistor 3 intermediate cascade connected to the input 10 of the buffer amplifier 11 and the collector of the third output transistor 12 of the intermediate stage, the emitter of which is connected to the emitter of the fourth 13 output transistor of the intermediate stage and the bus of the second power source 14, and the base is connected to the base of the fourth 13 output transistor of the intermediate stage and the collector of the first 2 output transistors of the intermediate stage.

A significant drawback of the known KDU (figure 1) is that it has a relatively large value of the emf of the zero offset, which negatively affects the static parameters of various analog devices based on it.

The main objective of the invention is to reduce the emf bias zero.

This goal is achieved by the fact that in the cascode differential amplifier of Fig. 1, containing the input differential stage 1, the first 2 and second 3 output transistors of the intermediate stage, the bases of which are connected to a bias voltage source 4, and the emitters are connected to the outputs 5 and 6 of the input differential stage 1 and through the first 7 and second 8 current-stabilizing two-pole connected to the bus of the first 9 power source, and the collector of the second output transistor 3 of the intermediate stage is connected to the input 10 of the buffer amplifier Yelaya 11 and the collector of the third output transistor 12 of the intermediate stage, the emitter of which is connected to the emitter of the fourth 13 output transistor of the intermediate stage and the bus of the second power supply 14, and the base is connected to the base of the fourth 13 output transistor of the intermediate stage and the collector of the first 2 output transistor of the intermediate stage new elements and connections - an additional transistor 15 is introduced into the circuit, the base of which is connected to a common bus of the first 9 and second 14 power sources, the collector is connected It is connected to the emitter of the first 2 output transistor of the intermediate stage, and the emitter is connected to the collector of the fourth 13 output transistor of the intermediate stage.

The amplifier circuit of the prototype is presented in figure 1. Figure 2 presents a diagram of the inventive device in accordance with claim 1 of the claims. Figure 3 and figure 4 shows a diagram of the known (figure 3) and the claimed (figure 4) devices in a computer simulation environment PSpice, and in figure 5, figure 6 - dependence of the voltage emf of the zero offset KDE of figure 4 on voltage an additional source of bias 16 in large (Fig. 5) and small (Fig. 6) scales.

The differential amplifier of figure 2 contains the input differential stage 1, the first 2 and second 3 output transistors of the intermediate stage, the bases of which are connected to a bias voltage source 4, and the emitters are connected to the outputs 5 and 6 of the input differential stage 1 and through the first 7 and second 8 are current stabilizing bipolar connected to the bus of the first 9 power source, and the collector of the second output transistor 3 of the intermediate stage is connected to the input 10 of the buffer amplifier 11 and the collector of the third output transistor 12 KSR stage, an emitter connected to the emitter of the fourth transistor 13 of the output of the intermediate stage and the second power supply bus 14, and the base connected to the base of the fourth output transistor 13 of the intermediate stage and the collector of the first output transistor 2 of the intermediate stage. An additional transistor 15 is introduced into the circuit, the base of which is connected to the common bus of the first 9 and second 14 power sources, the collector is connected to the emitter of the first 2 output transistor of the intermediate stage, and the emitter is connected to the collector of the fourth 13 output transistor of the intermediate stage.

In a particular case, the base of the additional transistor 15 can be connected to a common bus of power supplies 9 and 14 through an additional bias voltage source 16 (Fig. 2).

Consider the operation of the inventive cascode differential amplifier as an example of the analysis of the circuit of figure 2.

The static current mode of the KDU of FIG. 2 is set by the reference current source I ₀ in the emitter circuit of the input differential stage 1 and the current-stabilizing two-terminal 7 and 8. The currents in the circuit elements corresponding to the notation in the drawing of FIG. 2 are as follows:

where I _кij - collector currents of transistors;

I ₅ , I ₆ - static currents of outputs 5 and 6 of the control panel;

I ₀ is the static current of the common emitter circuit of the input differential stage 1;

β ₁₃ ≈ β ₁₂ - static current transfer coefficients of the base of transistors 13 and 12.

If β ₁₃ = β ₁₂ >> 1, then in

Static mode voltage of the collector-base transistors 13 and 12 (with the introduction of 100% feedback from the output of buffer amplifier 11 to the inverting input INP1 ^(-)) depends on the voltage on the base of transistor 15

where E ^(-) is the voltage of the power source 14.

Thus, due to the appropriate choice of the voltage of the additional bias source E ₁₆ at the level of E ₁₆ ≈U _eb.15, it is possible to obtain the same voltage U _kb.13 ≈U _kb.12 . This allows you to ensure the same bias of the input characteristics of the transistors 13 and 12, due to the influence of the Earley effect and, as a result, eliminate one of the main reasons for the appearance of a voltage KDU zero offset (E _cm ).

Computer simulation shows that in the scheme of the KDU prototype, the systematic component of the emf of the zero bias takes on a fairly large value: E _cm.n. = 4.4 mV (Fig. 4).

In the inventive device, the numerical values of E _cm depend on the voltage E ₁₆ (Fig. 5, Fig. 6). If E ₁₆ = 0, then E _cm . 3 = -103.7 μV. At E _cm . ₃ = 0.7 V, E _cm . ₃ = + 133 μV. The lowest values of E = 1.6 microvolts _seet3 obtained at E ₁₆ = 0.3 V. Thus, in Scheme 2 set conditions under which eliminates the systematic error amplification DC signals caused by the structural features of the DCD. This allows us to recommend the claimed circuit for use as part of precision interfaces. By choosing the voltage value E _16, it is possible to widely control the emf of the zero offset of the CDD.

BIBLIOGRAPHIC LIST

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Claims (2)

1. A cascode differential amplifier containing an input differential stage (1), first (2) and second (3) output transistors of the intermediate stage, the bases of which are connected to a bias voltage source (4), and the emitters are connected to outputs (5) and (6) ) of the input differential stage (1) and through the first (7) and second (8) current-stabilizing two-terminal circuits are connected to the bus of the first (9) power source, and the collector of the second output transistor (3) of the intermediate stage is connected to the input (10) of the buffer amplifier (11 ) and the third collector in the output transistor (12) of the intermediate stage, the emitter of which is connected to the emitter of the fourth (13) output transistor of the intermediate stage and the bus of the second power source (14), and the base is connected to the base of the fourth (13) output transistor of the intermediate stage and the collector of the first (2) output an intermediate stage transistor, characterized in that an additional transistor (15) is introduced into the circuit, the base of which is connected to a common bus of the first (9) and second (14) power sources, the collector is connected to the emitter of the first (2) output t anzistora intermediate stage, and an emitter - coupled to the collector of the fourth (13) output transistor of the intermediate stage. 2. The device according to claim 1, characterized in that the base of the additional transistor (15) is connected to a common bus of power sources (9) and (14) through an additional bias voltage source (16).

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