RU2040809C1 - Device for control of regeneration in semiconductor dynamic memory unit - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has first, second, third and fourth NAND gates 1-4, first and second flip-flops 5 and 6, first, second and third AND gates 8, 9, 10, first and second delay gates 10, 11, OR gate 12, NOT gate 13, regeneration start pulse generator 14, measuring detectors unit 15.1-15.k. EFFECT: increased functional capabilities. 2 cl, 1 dwg

Description

 The invention relates to computer technology and can be used in specialized computer systems that are exposed during operation to physical fields of increased and varying intensity, for example, in information-measuring systems for monitoring the radiological situation, X-ray and NMR tomographs, industrial robots, etc.

 With increased intensity of ionizing radiation and / or electromagnetic fields acting on the computer complex, it is necessary, first of all, to ensure the safety of the information recorded in the storage devices. This problem is most often solved by using semiconductor dynamic storage devices in computer complexes, which include dynamic RAM LSIs.

), и запрещается выдача строба адреса столбца (сигнала

). При этом для перебора всех строк необходимо наличие счетчика, а также схема коммутации его содержимого на адресные входы БИС ОЗУ с соответствующими элементами управления.A condition for storing information in dynamic LSI RAM is the need for periodic reference to each of the rows of the drive matrix. Usually, a regeneration mode is used for which, in each cycle of access to the LSI RAM, the address of the next line is supplied, followed by the strobe of the line address (signal

), and the strobe of the column address (signal

) At the same time, to search all the lines, it is necessary to have a counter, as well as a circuit for switching its contents to the address inputs of the BIS RAM with the corresponding controls.

и

, однако в отличие от обычной записи или чтения сигнал

следует раньше сигнала

. При этом работает внутренний счетчик БИС ОЗУ, который отсчитывает регенерируемые строки.In order to eliminate these hardware costs, the latest models of domestic and foreign BIS RAM have a special regeneration mode when both signals are sent to microcircuits

and

however, unlike normal recording or reading, the signal

follows before signal

. In this case, the internal LSI RAM counter works, which counts the regenerated lines.

A device for controlling regeneration in a semiconductor dynamic memory, providing control of the regeneration mode both in the absence of memory requests from external devices, and in their presence [1]
A known device for controlling regeneration in a semiconductor dynamic memory contains the first, second, third and fourth AND elements, the first and second triggers, the first, second and third AND elements, the first and second delay elements, the OR element and the NOT element, the first input of the first The NAND element is connected to the direct output of the first trigger, the synchronization input of which is the first synchronizing input of the device, the output of the second NAND element is connected to the installation input of the first trigger, whose inverse output is connected to the reset gate of the second trigger and the first input of the third AND-NOT element, the second input of which is the control input of the device, the first input of the fourth AND-NOT element is connected to the output of the first AND element and is the device start output, the first input of the second AND element is connected to the direct output of the second the trigger, the information input of which is the signal input of a logical unit of the device, the output of the first element is NOT connected to the first input of the third element And, the second input of which is the input of the first delay element are not connected to the output of the third AND element, the input of the second delay element and the first input of the first AND element are combined and connected to the output of the OR element, the first input of which and the element input are NOT combined and are the request input of the device, the output of the element is NOT connected to the first input the second AND-NOT element, the second input of which, the second input of the first AND-NOT element and the second input of the fourth AND-NOT element are combined and are the second clock input of the device, the third input of the second AND-NOT element is connected to the output of the second nta And, the second input of which is connected to the output of the first delay element, the output of the second delay element is connected to the second input of the first AND element, the output of the fourth AND-NOT element and the output of the third AND element are, respectively, the output of the gate of the address of the row and the output of the gate of the address of the column of the device, information the input of the first trigger is the input of the logical zero signal of the device, and the direct output of the first trigger is connected to the second input of the OR element. The device also contains a pulse generator connected to the synchronization input of the second trigger, the period of which determines the frequency of regeneration cycles.

 When determining the length of the repetition period of the start pulses of the regeneration mode, it is necessary to take into account that, firstly, during the operation of the LSI RAM, it cannot interact with other parts of the computing complex, whose operation is interrupted for the duration of the regeneration cycle. Secondly, the information stored in dynamic memory is destroyed over time, and therefore, to increase the noise immunity of the memory and increase the reliability of its operation, it is necessary to increase the frequency of starting the regeneration mode.

 When a semiconductor dynamic memory is exposed to ionizing radiation and / or strong electromagnetic fields, the rate of destruction of stored information increases. This, in turn, requires a reduction in the time interval between regeneration cycles, that is, an increase in the frequency of starting the regeneration mode. With a constant duration of the regeneration cycle, an increase in the start frequency of this mode leads to a redistribution of the total operating time of the dynamic memory in the direction of decreasing the time during which the dynamic memory can interact with other parts of the computing complex, which is equivalent to a decrease in the average effective speed of dynamic memory and, therefore, a decrease in performance computer complex.

 When operating a computer complex with dynamic memory in stable conditions, it is possible to select the optimal constant frequency of starting the regeneration mode, at which the required noise immunity and reliability of the memory are achieved with the minimum acceptable decrease in its average effective speed.

 In the case of exposure to a computer complex with a semiconductor dynamic memory of physical fields of varying intensity, maintaining a constant frequency of starting the regeneration mode when increasing the field intensity above the specified values can lead to disruption of the complex due to a sharp decrease in the reliability of the memory. The choice of an increased start frequency of the regeneration mode, oriented to the maximum peak values of the intensity of physical fields, leads to unjustified losses of machine time at medium and low intensity.

 The objective of the invention is to provide the ability to adapt the start frequency of the regeneration mode of the semiconductor dynamic memory to changes in the intensity of external physical fields, which, while maintaining the required noise immunity and reliability of the memory, can provide the average effective memory speed that is most acceptable by the current operating conditions.

 The specified technical result is achieved in that in a device for controlling regeneration in a semiconductor dynamic memory containing the first, second, third and fourth AND-NOT elements, the first and second triggers, the first, second and third AND elements, the first and second delay elements, the element OR and the element NOT, the first input of the first element AND is NOT connected to the direct output of the first trigger, the synchronization input of which is the first synchronizing input of the device, the output of the second element is NOT connected to the installation input first about the trigger, the inverse output of which is connected to the reset input of the second trigger and the first input of the third AND-NOT element, the second input of which is the control input of the device, the first input of the fourth AND-NOT element is connected to the output of the first AND element and is the device startup output, the first input the second element And is connected to the direct output of the second trigger, the information input of which is the signal input of the logical unit of the device, the output of the first element AND is NOT connected to the first input of the third element And, the second input to and the input of the first delay element is combined and connected to the output of the third AND element, NOT, the input of the second delay element and the first input of the first AND element are combined and connected to the output of the OR element, the first input of which and the input of the element are NOT combined and are the request input of the device, output of the element is NOT connected to the first input of the second AND-NOT element, the second input of which, the second input of the first NAND element and the second input of the fourth NAND element are combined and are the second clock input of the device, the third input is second about the AND element is NOT connected to the output of the second AND element, the second input of which is connected to the output of the first delay element, the output of the second delay element is connected to the second input of the first AND element, the output of the fourth AND element and the output of the third AND element are respectively the address gating output the line and the output of the gating of the column address of the device, the information input of the first trigger is the input of the logical zero signal of the device, and the direct output of the first trigger is connected to the second input of the OR element, a group of measuring sensors of the intensity of external physical fields and a block for generating pulses of the start of regeneration, the inputs of which are connected to the outputs of the measuring sensors of the intensity of external physical fields, and an output with the synchronization input of the second trigger. At the same time, the regeneration start-up pulse generation unit contains an integrator made on a differential operational amplifier, a comparator and an adjustable constant voltage source connected by one of its outputs to one of the summing inputs of the integrator, the remaining summing inputs of which are inputs of the unit, the integrator output is connected to the signal input of the comparator, the reference voltage input of which is connected to another output of the adjustable constant voltage source, and the comparator output connected to the input house reset the integrator is the output unit.

 A functional diagram of a device for controlling regeneration in a semiconductor dynamic memory is shown in the drawing.

) и выход 21 стробирования адреса столбца (выход сигнала

), управляющий вход 22.The device contains the first 1, second 2, third 3 and fourth 4 AND-NOT elements, first 5 and second 6 triggers, first 7, second 8 and third 9 AND elements, first 10 and second 11 delay elements, OR element 12 and NOT element 13, a unit 14 for generating regeneration start-up pulses and a group of measuring sensors 15.1 15.k of the intensity of external physical fields. The drawing also shows the first clock input 16, the output 17 start, request input 18, the second clock input 19, the output 20 of the gating address of the line (signal output

) and column address gating output 21 (signal output

), control input 22.

 A device for controlling regeneration in a semiconductor dynamic memory operates as follows.

 In the initial state, triggers 5 and 6 are zeroed, at the inputs 16 and 19 there are high voltage levels of logical units (Log. 1), and at inputs 18 and 22 there are low logic zeros (Log. 0), at the output of OR 12 and the output of AND 7 turn out to be a log. 0, and at the outputs of the elements AND NOT 1 and 3 log. 1. As a result, at the output 17 of the device there is a log. 0, and at the outputs 20 and 21 log. 1.

 If there are no memory requests on the next positive edge arriving at trigger synchronization input 6, the latter is set to unity, and the log. 1 from its direct output is fed to the first input of AND 8. Since its second input also contains a log. 1, a high level from the output of the AND 8 element goes to the third input of the AND-NOT 2 element. There is a log at the first two inputs of this element. 1, therefore, a log is generated at its output. 0, passing to the installation input of trigger 5. Trigger 5 goes to unity, and the log. 0 from its inverse output is issued to the reset input of trigger 6. The latter returns to the zero state, the output of AND 8 is the log. 0, and at the output of the element AND NOT 2 log. 1.

. Одновременно высокий уровень с прямого выхода триггера 5 поступает на второй вход элемента ИЛИ 12, проходит его и оказывается на первом входе элемента И 7 и входе элемента задержки 11. Время прохождения сигнала через элемент задержки 11 определяется интервалом между сигналами

и

в режиме регенерации, по окончании которого на втором входе элемента И 7 также оказывается высокий уровень напряжения. В результате на его выходе формируется лог. 1, выдаваемая на элемент И 8, в результате на его выходе формируется лог. 1, выдаваемая на выход 17 устройства в виде сигнала "Запуск". Последний поступает в формирователь синхросигналов ОЗУ, который может быть выполнен на основе регистра сдвига или линии задержки.The transition to trigger unit 5 (a single state of trigger 5 is a sign of a regeneration cycle) causes the appearance of a log. 1 at the first input of AND-NOT 1. Since the log is also present at the second input of this element. 1, a low voltage level is formed at its output, which, having passed the And 9 element, is output to the device output 21 as a signal

. At the same time, a high level from the direct output of trigger 5 goes to the second input of the OR element 12, passes it, and is at the first input of the And element 7 and the input of the delay element 11. The signal travel time through the delay element 11 is determined by the interval between signals

and

in regeneration mode, at the end of which a high voltage level also appears at the second input of the And 7 element. As a result, a log is formed at its output. 1, issued to element And 8, as a result, a log is generated at its output. 1, issued to the output 17 of the device in the form of a signal "Start". The latter enters the RAM driver, which can be performed based on a shift register or delay line.

, поступающий на синхронизирующий вход 16, и задержанный относительно него на некоторое время

, поступающий на синхронизирующий вход 19. Низкий уровень синхросигнала

проходит на вторые входы элементов И-НЕ 1 и 4 и вызывает появление на их входах лог. 1, что приводит к завершению выдачи сигналов

и

. Первый синхросигнал

поступает на вход синхронизации триггера 5 и, так как на его входе данных присутствует лог. 0, задним положительным фронтом возвращает триггер в нулевое состояние. Обнуление триггера 5 приводит к окончанию выдачи сигнала ЗАПУСК и гарантирует сохранение высоких уровней на выходах 20 и 21 устройства после завершения выдачи второго синхросигнала

.In response to the “Start” signal, the clock driver issues two clock signals to the device:

arriving at the synchronizing input 16, and delayed relative to it for a while

at sync input 19. Low sync

passes to the second inputs of AND-NOT elements 1 and 4 and causes a log to appear on their inputs. 1, which completes the signal output

and

. First clock

arrives at trigger synchronization input 5 and, since a log is present at its data input. 0, a trailing positive edge returns the trigger to the zero state. Zeroing the trigger 5 leads to the end of the issuance of the START signal and guarantees the preservation of high levels at the outputs 20 and 21 of the device after the completion of the second sync signal

.

. Для формирования сигнала

на вход 22 устройства подается высокий уровень управляемого сигнала УПР, задний фронт которого определяется моментом окончания записи или чтения данных из накопителя. Поскольку в циклах обслуживания внешних запросов триггер 5 сохраняет нулевое состояние, на первом входе элемента И-НЕ 3 присутствует лог. 1, и с приходом сигнала УПР на его выходе формируется лог. 0, в дальнейшем он через элемент И 9 выдается на выход 21 устройства в качестве сигнала

.If necessary, write or read information from the drive to the input 18 of the device receives a high signal level REQUEST. It goes to the first input of the OR element 12 and forms a log on its output. 1, then, similarly to the regeneration mode, START signals are issued to the outputs 17 and 20 of the device

. To generate a signal

at the input 22 of the device a high level of the control signal is fed, the trailing edge of which is determined by the moment the recording or reading data from the drive is completed. Since trigger 5 maintains a zero state in the service cycles of external requests, a log is present at the first input of the AND-NOT 3 element. 1, and with the arrival of the UPR signal, a log is generated at its output. 0, in the future it is transmitted through the And 9 element to the output 21 of the device as a signal

.

 There are two possible conflicts, between regeneration and external requests to the drive. The first drive request comes during the regeneration cycle; the second regeneration requirement (a positive voltage drop at the trigger synchronization input 6 occurs in the process of servicing a request to the drive).

, сигнал ЗАПУСК на выходе 17 остается в состоянии лог. 1, поэтому по окончании второго синхросигнала

, на обоих входах элемента И-НЕ 4 оказывается высокие уровни напряжения и на выход 20 выдается сигнал

, при этом длительность паузы между сигналами

, необходимая для нормальной работы БИС ОЗУ, определяется продолжительностью синхросигнала

. Выдача сигнала

на выход 21 осуществляется по управляющему сигналу УПР на входе 22 так же, как это было описано выше.If a request to the drive occurs during the regeneration cycle, then the log. 1 at the output of the OR element 12 is saved even after the trigger 5 is reset to zero along the trailing edge of the first clock signal

, the START signal at output 17 remains in the log state. 1, therefore, at the end of the second clock

, at both inputs of the AND-NOT 4 element there are high voltage levels and a signal is output 20

, while the duration of the pause between signals

necessary for the normal operation of the LSI RAM, is determined by the duration of the clock

. Signal output

the output 21 is carried out by the control signal UPR at the input 22 in the same way as described above.

 If the regeneration requirement arises during the drive access cycle, a high voltage level from the direct output of trigger 6 through element And 8 passes to the third input of AND-NOT 2. However, due to the presence of a high signal level, REQUEST at input 18, at the output of the element NOT 13 and the first input of the AND-NOT 2 element is a log. 0, therefore, the log is saved at the output of the AND-NOT 2 element. 1 and trigger 5 remains in the zero state. With the arrival of the control signal at both inputs of the AND-NOT 3 element, a log appears. 1, and on its output a log. 0. The latter passes the delay element 10, the And 8 element and goes to the third input of the AND-NOT 2 element, confirming the log. 1 at its output, as a result of the log. 1 at the output of the AND-NOT 2 element is also saved after removing the REQUEST signal from input 18.

и

согласно временной диаграмме, соответствующей режиму регенерации, при этом длительность паузы между сигналами, необходимая для нормальной работы БИС ОЗУ, определяется временем прохождения лог. 1 через элемент 10 задержки.At the end of writing or reading data from the drive, the control signal from input 22 is removed, and a log appears at the output of the AND-NOT 3 element. 1. Having passed the delay element 10 and the And 8 element, it enters the third input of the AND-NOT 2 element, at all three inputs of which there are high voltage levels. At the output of the AND-NOT 2 element, a log is formed. 0, and trigger 5 goes into a single state. As a result, START signals are issued to the device outputs,

and

according to the time diagram corresponding to the regeneration mode, while the duration of the pause between the signals necessary for the normal operation of the LSI RAM is determined by the time it takes for the log to pass. 1 through delay element 10.

, низкий уровень которого присутствует на втором входе элемента И-НЕ 2. Это позволяет завершить цикл записи или чтения данных до момента схемы признака цикла.In high-speed RAM, the EPR signal can be short and can be removed before the REQUEST signal. In this case, the installation in trigger unit 5 is delayed until the end of the clock signal

, the low level of which is present at the second input of the AND-NOT 2. element. This allows you to complete the cycle of writing or reading data to the point of the loop feature circuit.

 The frequency of the regeneration cycles is determined by the pulse repetition period from the pulse generation unit 14 of the regeneration start pulse, which can be used as a converter of the sum of the input voltages to the frequency. At the same time, the input voltage sources of block 14 are measuring sensors 15.1 15.k. Depending on the operating conditions of the semiconductor dynamic memory, the group of measuring sensors for the intensity of external physical fields may contain sensors for the intensity of α and β radiation, sensors for the intensity of the electromagnetic field, etc.

 The work of the above embodiment of the block 14 of the formation of pulses of the start of regeneration is as follows.

 A linearly increasing voltage is formed at the output of the integrator, the slope of which is determined both by the integrator's time constant and the input voltage values, and by the input coefficients of the corresponding integrator inputs. When the linearly increasing output voltage of the integrator reaches a level equal to the voltage supplied to the input of the reference voltage of the comparator, the latter is triggered, and a positive voltage drop appears at the output of block 14. The same signal, arriving at the reset input of the integrator, resets its output voltage, as a result of which the signal at the output of the comparator returns to zero level. Thus, at the output of the comparator, that is, at the output of block 14, pulses of positive polarity are formed, the minimum frequency of which is determined by the time constant of the integrator and the values of the voltage levels at the outputs of an adjustable constant voltage source.

 The voltage coming to the other inputs of the integrator from the outputs of the sensors 15.1 15.k increases the steepness of the output voltage of the integrator and, therefore, the frequency of the pulses at the output of the unit 14. In this case, the frequency of the pulses generated at the output of the unit 14 changes in accordance with changes in the output voltages of the sensors 15.1 15.k , that is, in accordance with the current values of the intensities of the physical fields controlled by the sensors.

 Thus, the device made according to the invention allows not only to resolve conflicts between drive requests and regeneration requirements and to regenerate using an internal counter of regenerated lines in the LSI RAM, but also adapts to the current operating conditions of the semiconductor dynamic memory, providing by automatic change the frequency of starting the regeneration mode; the achievement of the maximum allowable average operating speed of the memory allowed by operating conditions while maintaining the required noise immunity and reliability.

Claims (2)

 1. DEVICE FOR REGENERATION MANAGEMENT IN SEMICONDUCTOR DYNAMIC MEMORY, containing the first, second, third and fourth AND elements, the first and second triggers, the first, second and third AND elements, the first and second delay elements, the OR element and the NOT element, the first input the first AND element is NOT connected to the direct output of the first trigger, the synchronization input of which is the first synchronizing input of the device, the output of the second AND element is NOT connected to the installation input of the first trigger, whose inverse output is connected to the input throwing the second trigger and the first input of the third element AND NOT, the second input of which is the control input of the device, the first input of the fourth element AND is NOT connected to the output of the first element And is the output of the device starting, the first input of the second element And is connected to the direct output of the second trigger, information the input of which is the signal input of a logical unit of the device, the output of the first AND element is NOT connected to the first input of the third AND element, the second input of which and the input of the first delay element are combined and are connected with the output of the third element AND NOT, the input of the second delay element and the first input of the first AND element are combined and connected to the output of the OR element, the first input of which and the input of the element are NOT combined and are the request input of the device, the output of the element is NOT connected to the first input of the second AND element NOT, the second input of which, the second input of the first element AND NOT and the second input of the fourth element AND are NOT combined and are the second synchronizing input of the device, the third input of the second element AND is NOT connected to the output of the second element AND, the second input of which is connected with the output of the first delay element, the output of the second delay element is connected to the second input of the first AND element, the output of the fourth element AND NOT and the output of the third element AND are the output of the gate of the row address and the output of the gate of the column address of the device, the information input of the first trigger is the input of the logical zero signal of the device, and the direct output of the first trigger is connected to the second input of the OR element, characterized in that a group of measuring sensors are introduced into it intensity of external physical fields and a pulse generation block for triggering regeneration, the inputs of which are connected to the outputs of the measuring sensors of the intensity of external physical fields, and the output with the synchronization input of the second trigger.  2. The device according to claim 1, characterized in that the regeneration start-up pulse generation unit comprises an integrator made on a differential operational amplifier, a comparator and an adjustable constant voltage source connected by one of its outputs to one of the integrating inputs of the integrator, the remaining summing inputs of which are inputs unit, the output of the integrator is connected to the signal input of the comparator, the input of the reference voltage of which is connected to another output of an adjustable source of constant voltage, and the output One comparator connected to the reset input of the integrator is the output of the unit.