KR0183813B1 - DMA Refresh Controller - Google Patents
DMA Refresh Controller Download PDFInfo
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- KR0183813B1 KR0183813B1 KR1019960001099A KR19960001099A KR0183813B1 KR 0183813 B1 KR0183813 B1 KR 0183813B1 KR 1019960001099 A KR1019960001099 A KR 1019960001099A KR 19960001099 A KR19960001099 A KR 19960001099A KR 0183813 B1 KR0183813 B1 KR 0183813B1
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- refresh
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- dram
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- refresh controller
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- 230000003111 delayed effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
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- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
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Abstract
본 발명은 DRAM 리프레쉬 제어기에 관해 게시한다. 종래의 DRAM 리프레쉬 제어기는 메모리셀들이 활성화되어 있는 상태에 관계없이 일정한 시간마다 리프레쉬를 시켜주다 보니 불필요한 동작 시간이 소비되어 전체적인 신호 처리 속도가 지연되었으나, 본 발명의 DRAM 리프레쉬 제어기는 메모리셀들이 로우어드레스 신호에 의해 활성화되어 있는 경우에는 리프레쉬를 시켜주지 않기 때문에 그만큼 불필요한 동작을 방지하여 전체적인 신호 처리를 향상시킬 수 있다.The present invention relates to a DRAM refresh controller. The conventional DRAM refresh controller refreshes at regular intervals regardless of the state in which the memory cells are activated. As a result, unnecessary signal processing time is consumed and the overall signal processing speed is delayed. However, the DRAM refresh controller of the present invention has a low address. If it is activated by a signal, it is not refreshed, so that unnecessary operation can be prevented and the overall signal processing can be improved.
Description
제1도는 종래의 DRAM 리프레쉬(Refresh) 제어기의 블록도.1 is a block diagram of a conventional DRAM refresh controller.
제2도는 상기 제1도의 신호들의 타이밍도.2 is a timing diagram of the signals of FIG.
제3도는 본 발명의 DREAM 리프레쉬 제어기의 블록도.3 is a block diagram of a DREAM refresh controller of the present invention.
제4도는 상기 제3도의 신호들의 타이밍도.4 is a timing diagram of the signals of FIG.
본 발명은 DRAM 리프레쉬 제어기에 관한 것으로서, 특히 로우어드레스(Row Address)만 리프레쉬시키는 DRAM 리프레쉬 제어기에 관한것이다.The present invention relates to a DRAM refresh controller, and more particularly, to a DRAM refresh controller for refreshing only a low address.
DRAM을 사용하는 시스템에서는 DRAM에 저장된 데이터를 계속 유지하기 위하여 반드시 일정한 주기마다 DRAM을 리프레쉬시켜 주어야 한다. 그런데 DRAM을 리프레쉬시키는 데에는 두 가지 방식이 있는데 그것은 로우어드레스 리프레쉬(RAS only refresh)와 칼럼어드레스 리프레쉬(CAS before RAS refresh)이다. 본 발명은 로우어드레스 리프레쉬 방식에 관해 개선한 것이다.In a system using a DRAM, the DRAM must be refreshed at regular intervals to maintain the data stored in the DRAM. However, there are two ways to refresh the DRAM: low address refresh (RAS only refresh) and column address refresh (CAS before RAS refresh). The present invention is an improvement on the low address refresh method.
제1도는 종래의 DRAM 리프레쉬 제어기의 블록도이다. 그 구조는 타이머(1)와어드레스카운트(Address counter)(3) 및 DRAM 제어부(5)로 구성되어 있다. 클럭이 입력되면 타이머(1)는 리프레쉬 요청(Request)신호를 발생하여 일부는 DRAM 제어부(5)로, 일부는 어드레스 카운터(3)로 보낸다. 그러면 어드레스 카운터(3)에서는 리프레쉬시킬 메모리셀의 어드레스신호를 발생하고, 상기 어드레스신호에 지정된 메모리셀은 타이머(1)에서 발생된 리프레쉬 요청 신호에 의하여 리프레쉬된다.1 is a block diagram of a conventional DRAM refresh controller. The structure is composed of a timer 1, an address counter 3, and a DRAM control unit 5. FIG. When the clock is input, the timer 1 generates a refresh request signal, partly to the DRAM controller 5, and partly to the address counter 3. The address counter 3 then generates an address signal of the memory cell to be refreshed, and the memory cell specified in the address signal is refreshed by the refresh request signal generated by the timer 1.
제2도는 상기 제1도의 신호들의 타이밍도를 나타낸다. 리프레쉬 요청신호가 발생하면(로우어드레스)신호가 활성화(active)되어 있는 구간 동안 메모리셀들을 리프레쉬 시킨다.2 shows a timing diagram of the signals of FIG. When a refresh request signal occurs The memory cells are refreshed during the period in which the (low address) signal is active.
상술한 종래의 DRAM 리프레쉬 제어기는 현재 활성화된(Active)메모리셀에 무관하게 매 구간마다 리프레쉬 동작을 수행한다. 그런데 DRAM은 로우어드레스 신호라 활성화될 경우에 해당 로우어드레스의 메모리셀들은 이미 리프레쉬된 상태이다. 즉 리드(read) 또는 라이트(write) 동작을 수행할 경우, 현재 활성화되어 있는 로우어드레스의 메모리셀들에 대해서는 저절로 리프레쉬가 실시되기 때문에 현재 활성화되어 있는 로우어드레스에 해당하는 메모리셀들을 위해서 리프레쉬 시켜줄 필요가 없다.The conventional DRAM refresh controller described above performs a refresh operation every section regardless of the currently active memory cell. However, when the DRAM is a low address signal and activated, the memory cells of the low address are already refreshed. That is, when a read or write operation is performed, the memory cells of the currently activated low address are refreshed by themselves and thus need to be refreshed for the memory cells corresponding to the currently active low address. There is no.
따라서 본 발명의 목적은 활성화되어 있는 메모리셀들에 대해서는 리프레쉬를 시키지 않는 DRAM 리프레쉬 제어기를 제공하는 데 있다.Accordingly, an object of the present invention is to provide a DRAM refresh controller which does not refresh the activated memory cells.
상기 목적을 달성하기 위하여 본 발명은, 외부클럭에 의하여 리프레쉬 요청 신호를 발생하는 타이머와, 상기 리프레쉬 요청 신호를 입력으로 받아서 리프레쉬 어드레스 신호를 발생시키는 어드레스 카운터와, 상기 리프레쉬 어드레스 신호와 로우어드레스 신호를 비교하는 비교기와, 상기 비교기의 출력과 리프레쉬 요청 신호를 입력으로 받아서 논리연산 결과를 출력하는 논리게이트 및 상기 논리게이트와 어드레스카운터 및 로우어드레스 신호에 의해 제어되는 DRAM 제어부를 구비하는 DRAM 리프레쉬 제어기를 제공한다.In order to achieve the above object, the present invention provides a timer for generating a refresh request signal by an external clock, an address counter for receiving a refresh request signal to generate a refresh address signal, and a refresh address signal and a low address signal. A DRAM refresh controller includes a comparator for comparing, a logic gate configured to receive an output of the comparator and a refresh request signal, and output a logic operation result, and a DRAM controller controlled by the logic gate, an address counter, and a low address signal. do.
상기 논리게이트는 논리곱게이트(AND gate)인 것이 바람직하다. 상기 본 발명에 의하여 메모리 정치의 신호 처리 속도를 향상시킬 수 있다.The logic gate is preferably an AND gate. According to the present invention, it is possible to improve the signal processing speed of the memory set.
이하, 실시예를 통하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail through examples.
제3도는 본 발명의 DRAM 리프레쉬 제어기의 블록도를 나타낸다. 그 구조는 클럭을 입력으로 하는 타이머(21), 상기 타이머(21)에 연결된 어드레스 카운터(23), 상기 어드레스 카운터(23)의 출려겨 신호와 로우어드레스 신호를 비교하는 비교기(25), 상기 비교기(25)의 출력 신호와 타이머(21)의 출력 신호를 논리곱연산하는 논리곱게이트(AND gate)(27) 및 DRAM 제어부(29)로 구성된다.3 shows a block diagram of a DRAM refresh controller of the present invention. The structure includes a timer 21 for inputting a clock, an address counter 23 connected to the timer 21, a comparator 25 for comparing a pulled-out signal and a low address signal of the address counter 23, and the comparator. And an AND gate 27 and an DRAM control unit 29 for performing an AND operation on the output signal of the timer 25 and the output signal of the timer 21.
제3도의 동작 상태를 살펴보면, 클럭을 받은 타이머(21)가 리프레쉬 요청 신호를 발생하면 상기 리프레쉬 요청 신호의 일부가 어드레스 카운터(23)로 입력된다. 그러면 상기 어드레스 카운터(23)는 리프레쉬시켜야 할 어드레스 신호를 발생하게 되고 이것은 비교기(25)에서 로우어드레스 신호와 비교되고 그 결과가 상기 어드레스 요청 신호와 함께 논리곱연산되어 DRAM 제어부(29)로 입력된다. 상기 과정에서 로우어드레스가 활성화되어 있는 경우, 비교기(25)에서는 출력 신호를 발생하지 않기 때문에 논리곱게이트(27)의 출력도 '0'상태가 되어 설사 타이머(21)에서 리프레쉬 요청 신호를 발생하더라도 활성화되어 있는메모리셀들은 리프레쉬되지 않는다.Referring to the operation state of FIG. 3, when the clocked timer 21 generates the refresh request signal, a part of the refresh request signal is input to the address counter 23. Then, the address counter 23 generates an address signal to be refreshed, which is compared with the low address signal in the comparator 25, and the result is ANDed together with the address request signal and input to the DRAM controller 29. . When the low address is activated in the above process, since the comparator 25 does not generate an output signal, the output of the logical product gate 27 also becomes '0' state, even if the refresh request signal is generated by the timer 21. Active memory cells are not refreshed.
제4도는 상기 제3도의 신호들의 타이밍도이다. 활성화되어 있는 로우어드레스 신호에 의해 활성되어 있는 메모리셀들을 위해서는 리프레쉬 신호가 발생되지 않기 때문에 상기 메모리셀들은 방해받지 않고 기존 동작을 계속 수행하게 된다. 그러므로 리프레쉬를 수행할 때 요구되는 동작들이 모두 생략되어서 그만큼 전체 회로의 동작 시간이 빨라지게 된다.4 is a timing diagram of the signals of FIG. Since the refresh signal is not generated for the memory cells activated by the activated low address signal, the memory cells continue to perform the existing operation without being interrupted. Therefore, all the operations required when performing the refresh are omitted so that the operation time of the entire circuit is shortened.
상술한 본 발명에 따르면 이미 활성화되어 있는 메모리셀들에 대해서는 리프레쉬 동작이 생략됨으로써 메모리 장치의 신호 처리 속도를 향상시킬 수가 있다.According to the present invention described above, the refresh operation is omitted for memory cells that are already activated, thereby improving the signal processing speed of the memory device.
본 발명은 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960001099A KR0183813B1 (en) | 1996-01-19 | 1996-01-19 | DMA Refresh Controller |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960001099A KR0183813B1 (en) | 1996-01-19 | 1996-01-19 | DMA Refresh Controller |
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| Publication Number | Publication Date |
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| KR970060225A KR970060225A (en) | 1997-08-12 |
| KR0183813B1 true KR0183813B1 (en) | 1999-04-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019960001099A KR0183813B1 (en) | 1996-01-19 | 1996-01-19 | DMA Refresh Controller |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100317198B1 (en) * | 1999-12-29 | 2001-12-24 | 박종섭 | Refresh circuit |
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1996
- 1996-01-19 KR KR1019960001099A patent/KR0183813B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100317198B1 (en) * | 1999-12-29 | 2001-12-24 | 박종섭 | Refresh circuit |
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| Publication number | Publication date |
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| KR970060225A (en) | 1997-08-12 |
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