NL8102650A - Logische rekeneenheid bedoeld voor het behandelen van bits. - Google Patents
Logische rekeneenheid bedoeld voor het behandelen van bits. Download PDFInfo
- Publication number
- NL8102650A NL8102650A NL8102650A NL8102650A NL8102650A NL 8102650 A NL8102650 A NL 8102650A NL 8102650 A NL8102650 A NL 8102650A NL 8102650 A NL8102650 A NL 8102650A NL 8102650 A NL8102650 A NL 8102650A
- Authority
- NL
- Netherlands
- Prior art keywords
- bit
- destination
- word
- state
- register
- Prior art date
Links
- 238000006073 displacement reaction Methods 0.000 claims description 35
- 230000004044 response Effects 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 claims description 3
- 230000008859 change Effects 0.000 claims description 2
- 239000005862 Whey Substances 0.000 claims 1
- 102000007544 Whey Proteins Human genes 0.000 claims 1
- 108010046377 Whey Proteins Proteins 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 13
- 230000006870 function Effects 0.000 description 2
- 238000010977 unit operation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
- G06F7/762—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data having at least two separately controlled rearrangement levels, e.g. multistage interconnection networks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30018—Bit or string instructions
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/155,317 US4525776A (en) | 1980-06-02 | 1980-06-02 | Arithmetic logic unit arranged for manipulating bits |
| US15531780 | 1980-06-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| NL8102650A true NL8102650A (nl) | 1982-01-04 |
Family
ID=22554951
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| NL8102650A NL8102650A (nl) | 1980-06-02 | 1981-06-01 | Logische rekeneenheid bedoeld voor het behandelen van bits. |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4525776A (de) |
| JP (1) | JPS5794852A (de) |
| DE (1) | DE3121046A1 (de) |
| FR (1) | FR2483656B1 (de) |
| GB (1) | GB2079502B (de) |
| NL (1) | NL8102650A (de) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4748580A (en) * | 1985-08-30 | 1988-05-31 | Advanced Micro Devices, Inc. | Multi-precision fixed/floating-point processor |
| US4775952A (en) * | 1986-05-29 | 1988-10-04 | General Electric Company | Parallel processing system apparatus |
| JP2565495B2 (ja) * | 1986-08-27 | 1996-12-18 | 株式会社日立製作所 | デ−タ処理システム |
| FR2656710A1 (fr) * | 1989-12-29 | 1991-07-05 | Radiotechnique Compelec | Microcontroleur pour l'execution rapide d'un grand nombre d'operations decomposable en sequence d'operations de meme nature. |
| US5327571A (en) * | 1990-04-03 | 1994-07-05 | Advanced Micro Devices, Inc. | Processor having decoder for decoding unmodified instruction set for addressing register to read or write in parallel or serially shift in from left or right |
| JPH06230960A (ja) * | 1993-01-29 | 1994-08-19 | Mitsubishi Electric Corp | データ処理回路 |
| JP2932963B2 (ja) * | 1994-01-21 | 1999-08-09 | モトローラ・インコーポレイテッド | 効率的なビット移動能力を有するデータ・プロセッサとその方法 |
| US6061783A (en) * | 1996-11-13 | 2000-05-09 | Nortel Networks Corporation | Method and apparatus for manipulation of bit fields directly in a memory source |
| US7031776B2 (en) * | 2001-06-29 | 2006-04-18 | Optobionics | Methods for improving damaged retinal cell function |
| US20050033202A1 (en) * | 2001-06-29 | 2005-02-10 | Chow Alan Y. | Mechanically activated objects for treatment of degenerative retinal disease |
| US8275978B1 (en) * | 2008-07-29 | 2012-09-25 | Marvell International Ltd. | Execution of conditional branch instruction specifying branch point operand to be stored in jump stack with branch destination for jumping to upon matching program counter value |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3982229A (en) * | 1975-01-08 | 1976-09-21 | Bell Telephone Laboratories, Incorporated | Combinational logic arrangement |
| US4212076A (en) * | 1976-09-24 | 1980-07-08 | Giddings & Lewis, Inc. | Digital computer structure providing arithmetic and boolean logic operations, the latter controlling the former |
| US4194241A (en) * | 1977-07-08 | 1980-03-18 | Xerox Corporation | Bit manipulation circuitry in a microprocessor |
-
1980
- 1980-06-02 US US06/155,317 patent/US4525776A/en not_active Expired - Lifetime
-
1981
- 1981-05-27 DE DE3121046A patent/DE3121046A1/de active Granted
- 1981-05-27 GB GB8116107A patent/GB2079502B/en not_active Expired
- 1981-05-29 FR FR8110707A patent/FR2483656B1/fr not_active Expired
- 1981-06-01 NL NL8102650A patent/NL8102650A/nl not_active Application Discontinuation
- 1981-06-02 JP JP56083928A patent/JPS5794852A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| GB2079502A (en) | 1982-01-20 |
| GB2079502B (en) | 1984-07-11 |
| FR2483656B1 (fr) | 1987-06-26 |
| FR2483656A1 (fr) | 1981-12-04 |
| US4525776A (en) | 1985-06-25 |
| DE3121046A1 (de) | 1982-03-11 |
| JPH0447335B2 (de) | 1992-08-03 |
| DE3121046C2 (de) | 1992-03-05 |
| JPS5794852A (en) | 1982-06-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR880000298B1 (ko) | 멀티워어드 메모리 데이타 스토리지 및 어드레싱 기법및 장치 | |
| US4779192A (en) | Vector processor with a synchronously controlled operand fetch circuits | |
| US5093783A (en) | Microcomputer register bank accessing | |
| US5726923A (en) | Minimum/maximum data detector | |
| NL8102650A (nl) | Logische rekeneenheid bedoeld voor het behandelen van bits. | |
| JPS59174948A (ja) | 情報処理装置 | |
| US4734877A (en) | Vector processing system | |
| US4394735A (en) | Data processor controlled by microprograms | |
| EP0122739B1 (de) | Steuergerät für Listenvektor | |
| US4688191A (en) | Single bit storage and retrieval with transition intelligence | |
| US4947358A (en) | Normalizer for determining the positions of bits that are set in a mask | |
| JPH03269728A (ja) | パイプライン計算機における命令実行制御方式 | |
| JPH02126321A (ja) | 命令コードのデコード装置 | |
| JPH07111683B2 (ja) | タスク切換機能付プロセッサ | |
| JP2812610B2 (ja) | パイプライン制御方式 | |
| JP2760649B2 (ja) | 情報処理装置 | |
| JPH0310129B2 (de) | ||
| JPS5880740A (ja) | マイクロプログラム制御装置 | |
| SU879564A1 (ru) | Устройство дл контрол программ | |
| KR20010072505A (ko) | 다수의 처리 및 메모리 회로를 포함하는 데이터 처리장치, 그 구성 방법 및 컴퓨터 프로그램 제품 | |
| JPS59216252A (ja) | 情報処理装置 | |
| AU634781B2 (en) | Normalizer | |
| JPH0311423A (ja) | ストリングデータ処理機構 | |
| JPH0749779A (ja) | インターリーブ装置及び方法 | |
| JPH02216581A (ja) | 情報処理装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A85 | Still pending on 85-01-01 | ||
| BA | A request for search or an international-type search has been filed | ||
| BB | A search report has been drawn up | ||
| BC | A request for examination has been filed | ||
| BV | The patent application has lapsed |