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NL1023020A1 - Bewakingswerkwijze, belichtingswerkwijze, een vervaardigingswerkwijze voor een halfgeleider-inrichting omvattende een etswerkwijze en een belichtingsverwerkingseenheid. - Google Patents

Bewakingswerkwijze, belichtingswerkwijze, een vervaardigingswerkwijze voor een halfgeleider-inrichting omvattende een etswerkwijze en een belichtingsverwerkingseenheid.

Info

Publication number
NL1023020A1
NL1023020A1 NL1023020A NL1023020A NL1023020A1 NL 1023020 A1 NL1023020 A1 NL 1023020A1 NL 1023020 A NL1023020 A NL 1023020A NL 1023020 A NL1023020 A NL 1023020A NL 1023020 A1 NL1023020 A1 NL 1023020A1
Authority
NL
Netherlands
Prior art keywords
exposure
manufacturing
processing unit
semiconductor device
etching
Prior art date
Application number
NL1023020A
Other languages
English (en)
Other versions
NL1023020C2 (nl
Inventor
Masafumi Asano
Nobuhiro Komine
Soichi Inoue
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of NL1023020A1 publication Critical patent/NL1023020A1/nl
Application granted granted Critical
Publication of NL1023020C2 publication Critical patent/NL1023020C2/nl

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Drying Of Semiconductors (AREA)
  • Length Measuring Devices By Optical Means (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
NL1023020A 2002-03-26 2003-03-26 Bewakingswerkwijze, belichtingswerkwijze, een vervaardigingswerkwijze voor een halfgeleider-inrichting omvattende een etswerkwijze en een belichtingsverwerkingseenheid. NL1023020C2 (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002087015A JP3727895B2 (ja) 2002-03-26 2002-03-26 モニタ方法
JP2002087015 2002-03-26

Publications (2)

Publication Number Publication Date
NL1023020A1 true NL1023020A1 (nl) 2003-09-29
NL1023020C2 NL1023020C2 (nl) 2005-12-28

Family

ID=28449347

Family Applications (1)

Application Number Title Priority Date Filing Date
NL1023020A NL1023020C2 (nl) 2002-03-26 2003-03-26 Bewakingswerkwijze, belichtingswerkwijze, een vervaardigingswerkwijze voor een halfgeleider-inrichting omvattende een etswerkwijze en een belichtingsverwerkingseenheid.

Country Status (6)

Country Link
US (1) US6866976B2 (nl)
JP (1) JP3727895B2 (nl)
KR (1) KR100572940B1 (nl)
CN (2) CN100582934C (nl)
NL (1) NL1023020C2 (nl)
TW (1) TWI241463B (nl)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4212421B2 (ja) * 2003-06-26 2009-01-21 株式会社東芝 マスク、露光量調整方法及び半導体デバイスの製造方法
JP2005197362A (ja) 2004-01-05 2005-07-21 Toshiba Corp 露光処理システムおよび露光処理方法
JP4373877B2 (ja) * 2004-08-09 2009-11-25 株式会社東芝 プロセス管理方法、モニターマーク形成方法及びプロセス管理用のマスク
KR100593745B1 (ko) * 2004-12-17 2006-06-28 삼성전자주식회사 캐패시터의 스토리지 노드 형성방법
JP2007227570A (ja) * 2006-02-22 2007-09-06 Toshiba Corp 製造装置調整システム及び製造装置調整方法
JP4825569B2 (ja) * 2006-04-12 2011-11-30 株式会社東芝 測定座標設定システム及び測定座標設定方法
JP2008218516A (ja) * 2007-02-28 2008-09-18 Toshiba Corp パターン評価方法、評価マーク、それを用いた半導体装置の製造方法
KR101118684B1 (ko) 2009-03-06 2012-03-06 한국과학기술원 측정 패턴 구조체, 보정 구조체, 기판 처리 장치, 및 기판 처리 방법
US8313877B2 (en) * 2009-06-12 2012-11-20 Micron Technology, Inc. Photolithography monitoring mark, photolithography mask comprising an exposure monitoring mark, and phase shift mask comprising an exposure monitoring mark
JP5391055B2 (ja) * 2009-12-25 2014-01-15 東京エレクトロン株式会社 半導体装置の製造方法及び半導体装置の製造システム
JP2012023215A (ja) * 2010-07-14 2012-02-02 Nikon Corp 露光量演算方法、並びに露光方法及び装置
JP5786940B2 (ja) * 2011-07-15 2015-09-30 コニカミノルタ株式会社 ガスバリア性フィルム及びその製造方法
US9006909B2 (en) 2013-01-03 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Solder mask shape for BOT laminate packages
TWI721371B (zh) * 2013-12-26 2021-03-11 日商旭化成電子材料股份有限公司 感光性樹脂組合物及感光性樹脂積層體
US9716013B2 (en) * 2014-02-04 2017-07-25 Texas Instruments Incorporated Sloped photoresist edges for defect reduction for metal dry etch processes
US20160004983A1 (en) * 2014-07-07 2016-01-07 GM Global Technology Operations LLC Method and apparatus for quantifying dimensional variations and process capability independently of datum points
CN106707697B (zh) * 2017-01-04 2018-10-26 上海华虹宏力半导体制造有限公司 芯片的图形尺寸检测方法
KR102620864B1 (ko) * 2018-11-23 2024-01-04 에스케이하이닉스 주식회사 반도체 패키지 및 제조 방법
CN110533662B (zh) 2019-09-19 2022-05-20 京东方科技集团股份有限公司 一种成像质量分析方法及其装置
US12210279B2 (en) * 2021-05-27 2025-01-28 AGC Inc. Electroconductive-film-coated substrate and reflective mask blank
US12066658B2 (en) * 2022-04-21 2024-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated optical devices and methods of forming the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06260383A (ja) * 1993-03-03 1994-09-16 Nikon Corp 露光方法
JPH10270320A (ja) 1997-03-25 1998-10-09 Sony Corp 露光装置および露光方法
JP3761357B2 (ja) * 1999-02-22 2006-03-29 株式会社東芝 露光量モニタマスク、露光量調整方法及び半導体装置の製造方法
US6238936B1 (en) * 1999-03-08 2001-05-29 Advanced Micro Devices, Inc. Method of using critical dimension mapping to qualify a new integrated circuit fabrication etch process
US6331711B1 (en) * 1999-08-06 2001-12-18 Etec Systems, Inc. Correction for systematic, low spatial frequency critical dimension variations in lithography
JP3949853B2 (ja) 1999-09-28 2007-07-25 株式会社東芝 露光装置の制御方法及び半導体製造装置の制御方法
JP4158384B2 (ja) * 2001-07-19 2008-10-01 株式会社日立製作所 半導体デバイスの製造工程監視方法及びそのシステム

Also Published As

Publication number Publication date
KR20030077465A (ko) 2003-10-01
JP2003282663A (ja) 2003-10-03
TW200402601A (en) 2004-02-16
US6866976B2 (en) 2005-03-15
NL1023020C2 (nl) 2005-12-28
CN1808270A (zh) 2006-07-26
TWI241463B (en) 2005-10-11
JP3727895B2 (ja) 2005-12-21
CN100582934C (zh) 2010-01-20
US20030215724A1 (en) 2003-11-20
CN1447194A (zh) 2003-10-08
CN1252543C (zh) 2006-04-19
KR100572940B1 (ko) 2006-04-25

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RD2N Patents in respect of which a decision has been taken or a report has been made (novelty report)

Effective date: 20050822

PD2B A search report has been drawn up
V1 Lapsed because of non-payment of the annual fee

Effective date: 20141001