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KR970053087A - 반도체 소자의 트랜지스터 제조방법 - Google Patents

반도체 소자의 트랜지스터 제조방법 Download PDF

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Publication number
KR970053087A
KR970053087A KR1019950066007A KR19950066007A KR970053087A KR 970053087 A KR970053087 A KR 970053087A KR 1019950066007 A KR1019950066007 A KR 1019950066007A KR 19950066007 A KR19950066007 A KR 19950066007A KR 970053087 A KR970053087 A KR 970053087A
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South Korea
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forming
polysilicon
depositing
heat treatment
film
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KR1019950066007A
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KR0172788B1 (ko
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이길호
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김주용
현대전자산업 주식회사
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Priority to KR1019950066007A priority Critical patent/KR0172788B1/ko
Priority to US08/768,940 priority patent/US5683920A/en
Priority to JP8343886A priority patent/JP2802263B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자의 트랜지스터 제조방법에 관한 것으로, 듀얼게이트 전극중 P형 게이트 전극을 형성하면서 게이트 전극이 형성될 부위이외의 폴리실리콘을 확산원으로 해서 소오스/드레인 영역에 붕소를 확산시켜 결함이 없는 초저접합을 형성하여 우수한 전기적 특성을 지닌 초고집적 소자 제조가 가능한 반도체 소자의 트랜지스터 제조방법에 관한 것이다.

Description

반도체 소자의 트랜지스터 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2f도는 본 발명에 따른 트랜지스터 제조 공정도.

Claims (9)

  1. 실리콘 기판상의 소정영역에 n-웰과 p-웰 및 소자 분리막을 차례로 형성한 후 게이트 산화막을 형성하는 단계와, 전체구조 상부에 폴리실리콘을 소정두께로 증착하는 단계와, 감광막을 p형 모스 전계 트랜지스터 상단부위에 소정두께 증착하는 단계와, 노출된 상기 폴리실리콘내로 인 이온을 주입하는 단계와, n형 모스 전계 트랜지스터 상단부위에 감광막을 증착하는 단계와, 노출된 폴리실리콘내로 붕소 이온을 주입하는 단계와, p형 게이트 전극이 형성될 부위와 n형 게이트가 형성될 부위의 상단에 감광막 패턴을 각각 형성하는 단계와, 전체구조 상부에 불화붕소를 주입하는 단계와, 상기 감광막 패턴을 제거한 후 질소분위기에서 일정시간 열처리하는 단계와, 게이트 전극 향성을 위해 감광막을 입힌후 식각을 통해 n형 및 p형 게이트 전극을 형성하는 단계와, 상기 게이트 전극의 측벽에 스페이서 산화막을 형성하는 단계와, n-웰측 부위의 상부에 감광막을 증착한 후 비소이온을 주입하여 n+소오스/드레인을 형성하는 단계와, 전체구조 상부에 제1층간 절연막과 제2층간 절연막을 차례로 형성하는 단계와, 상기 절연막 평탄화를 위해 소정온도에서 일정시간동안 질소분위기에서 열처리하는 단계를 구비하는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.
  2. 제1항에 있어서, 상기 게이트 산화막은 열산화 방식으로 30~60Å 두께로 형성하는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.
  3. 제1항에 있어서, 상기 게이트 산화막 상부에 증착되는 폴리실리콘의 두께는 1500~2500Å인 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.
  4. 제3항에 있어서, 상기 폴리실리콘은 같은 두께의 비정질 실리콘으로 대체될 수 있는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.
  5. 제1항에 있어서, 상기 인이온 주입시 40KeV～60KeV의 에너지로 3×1015/㎝2～1×1016/㎝2주입량으로 하는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.
  6. 제1항에 있어서, 상기 폴리실리콘상에 붕소 이온주입시, 15KeV~30KeV의 에너지와, 3×1015/㎝2~1×1016/㎝2주입량으로 주입하는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.
  7. 제1항에 있어서, 불화붕소 이온주입시 사용된 감광막 제거후 실시되는 열처리는 850℃~900℃ 사이의 온도에서 30~60분 동안 질소분위기에서 이뤄지는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.
  8. 제1항 또는 제7항에 있어서, 상기 열처리는 1000℃~1100℃에서 10초~30초간 급속 열처리로 실시되는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.
  9. 제1항에 있어서, 상기 절연막 평탄화를 위한 열처리는 800℃～850℃ 온도범위에서 30～60분간 질소분위기에서 실시되는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950066007A 1995-12-29 1995-12-29 반도체 소자의 트랜지스터 제조방법 Expired - Fee Related KR0172788B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950066007A KR0172788B1 (ko) 1995-12-29 1995-12-29 반도체 소자의 트랜지스터 제조방법
US08/768,940 US5683920A (en) 1995-12-29 1996-12-18 Method for fabricating semiconductor devices
JP8343886A JP2802263B2 (ja) 1995-12-29 1996-12-24 半導体素子の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950066007A KR0172788B1 (ko) 1995-12-29 1995-12-29 반도체 소자의 트랜지스터 제조방법

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KR970053087A true KR970053087A (ko) 1997-07-29
KR0172788B1 KR0172788B1 (ko) 1999-03-30

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US (1) US5683920A (ko)
JP (1) JP2802263B2 (ko)
KR (1) KR0172788B1 (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2988414B2 (ja) * 1997-02-20 1999-12-13 日本電気株式会社 半導体装置の製造方法
US6153456A (en) * 1998-01-14 2000-11-28 Vlsi Technology, Inc. Method of selectively applying dopants to an integrated circuit semiconductor device without using a mask
KR100498607B1 (ko) * 1998-06-30 2005-09-14 주식회사 하이닉스반도체 반도체 소자의 폴리실리콘층 형성방법
KR100308133B1 (ko) * 1999-01-12 2001-09-26 김영환 듀얼 게이트 모스 트랜지스터 제조방법
US6022771A (en) * 1999-01-25 2000-02-08 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions and sidewall spacers creating taper-shaped isolation where the source and drain regions meet the gate regions
US5998248A (en) * 1999-01-25 1999-12-07 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions with tapered spacer in isolation region
US5998273A (en) * 1999-01-25 1999-12-07 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions
US6025242A (en) * 1999-01-25 2000-02-15 International Business Machines Corporation Fabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolation
JP2001210726A (ja) * 2000-01-24 2001-08-03 Hitachi Ltd 半導体装置及びその製造方法
KR100505068B1 (ko) * 2003-07-05 2005-07-29 삼성전자주식회사 반도체 소자의 다중 게이트 산화막 및 이를 포함하는게이트 전극 형성방법
KR100783283B1 (ko) * 2006-12-05 2007-12-06 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조 방법
KR101012180B1 (ko) * 2008-09-03 2011-02-07 주식회사 동부하이텍 반도체 소자의 층간 절연막 형성 방법
CN112748640A (zh) * 2019-10-31 2021-05-04 浙江大学 一种场效应细胞培养皿的制备流程

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US4786611A (en) * 1987-10-19 1988-11-22 Motorola, Inc. Adjusting threshold voltages by diffusion through refractory metal silicides
US4948745A (en) * 1989-05-22 1990-08-14 Motorola, Inc. Process for elevated source/drain field effect structure
JPH0758701B2 (ja) * 1989-06-08 1995-06-21 株式会社東芝 半導体装置の製造方法
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JP3211394B2 (ja) * 1992-08-13 2001-09-25 ソニー株式会社 半導体装置の製造方法
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JP2802263B2 (ja) 1998-09-24
JPH09186245A (ja) 1997-07-15
KR0172788B1 (ko) 1999-03-30
US5683920A (en) 1997-11-04

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