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KR960043145A - 점유면적의 저감된 패드 배치를 가지는 반도체 기억장치 및 그를 위한 패드 배치 방법 - Google Patents

점유면적의 저감된 패드 배치를 가지는 반도체 기억장치 및 그를 위한 패드 배치 방법 Download PDF

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KR960043145A
KR960043145A KR1019960013507A KR19960013507A KR960043145A KR 960043145 A KR960043145 A KR 960043145A KR 1019960013507 A KR1019960013507 A KR 1019960013507A KR 19960013507 A KR19960013507 A KR 19960013507A KR 960043145 A KR960043145 A KR 960043145A
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pads
semiconductor
pad
leads
chip
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KR100218875B1 (ko
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마사끼 추쿠데
카쭈타미 아리모토
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기다오까 다까시
미쓰비시 뎅끼 가부시끼가이샤
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Abstract

장변(LS)과 단변(SS)을 가지는 반도체 칩(1)의 표면에 십자 형상으로 복수의 제1의 패드(PDa-PDp)의 열 및 복수의 제2의 패드(DPa-DPg)를 배치한다.
다비트 전개시에서, 패드수가 증가하여도 이 제2의 패드를 추가적으로 배설하는 것에 의해, 반도체 칩(1)이 장변 길이의 증가를 억제 할 수 있다. 또 이 때 하등 패드의 피치를 축소할 필요는 없다.
칩 및 패드 사이즈의 증가 및 패드 및 핀의 피치의 축소를 수반하는 것 없이 다비트 전개를 행할 수 있는 반도체 기억 장치가 제공된다.

Description

점유면적의 저감된 패드 배치를 가지는 반도체 기억장치 및 그를 위한 패드 배치 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1의 실시예인 반도체 기억장치의 내부배치를 표시.

Claims (20)

  1. 반도체 칩 상에 십자 형상으로 배치되는 장치 외부의 전기적 접속을 실현하기 위한 복수의 제1의 패드 (PDa-PDp : PA1-PA16 : PDa1-PDa2, PDb1-PDb2 : PL)의 열 및 복수이 제2패드(DPa-DPg : PB1-PB16 : PDc1-PDc2, PDd1, PDd2 : PS)의 열 및 복수의 제2패드(DPa-DPg : PB1-PB16 : PDc1-PDc2, PDd1, PDd2 : PS)의 열을 구비하는 반도체 기억장치.
  2. 제1항에 있어서 상기 칩상에 걸쳐서 배설되어 각각이 상기 반도체 칩의 제1의 변의 한편 측 또는 다른 편 측에 배치되는 한편 단과, 상기 제1 및 제2의 패드의 사정에 정하게 된 대응의 패드에 접속하는 다른 편 단을 가지는 복수의 리드(FL1a-FL18b)를 더 구비하는 반도체 기억장치.
  3. 제1항에 있어서, 상기 반도체 칩의 4변에 따라 배설되는 외부리드 단자에 대응하여 배치되어 각각이 상기 4변 중의 어느 것의 변에 배설 되는 한편 단과 상기 제1 및 제2의 패드의 사전에 정하게 된 대응의 패드에 접속되는 다른편 단을 가지는 상기 칩 상에 걸쳐서 연장하여 밸치되는 복수의 리드 FL1a-FL18b : FLa1-FLd4)를 더 구비하는 반도체 기억장치.
  4. 제1항에 있어서, 상기 복수의 제1의 패드(PDa-PDp)는 데이터를 입출력하기 위한 패트(DQ)를 포함하고, 상기 복수의 제2의 패드(PDa-PDg)는 외부에서 제공되는 제어신호 및 어드레스 신호를 받는 패드(DPa-DPf)를 포함하는 반도체 기억장치.
  5. 제2항에 있어서, 상기 제1의 변 방향의 중앙부에 배치되는 한편 단을 가지는 리드(FL6a-FL13a, FL6b-FL13b)는 상기 제2의 패드(PB1-PB16 : PDa1-PFa2) 되는 한편 단을 가지는 리드 (FL1a-FL5a, FL14a-FL18a, FL1b-FL5b, FL14b-FL18b)는 상기 제1의 패드(PA1-PA16 : PDc1, PDd1)에 접속되는 반도체 기억장치.
  6. 제5항에 있어서, 상기 제1의 변 방향과 직교하는 방향에 따라 배치되는 한편 단을 가지는 리드(FLd1, - FLd4 : FLc1-FLc4)는 상기 제1의 패드(PDc2, PDd2)에 접속되는 반도체 기억 장치.
  7. 제2항에 있어서 상기 제1의 변 방향의 중앙부에 배치되는 한편 단을 가지는 리드(FL6a-FL13a, FL6b-FL13b)는 상기 중앙부에서 단부로 향하여 배치되는 리드가 순차 상기 제2의 중앙영역에 외주부에서 내부로 향하여 배치되는 제2의 패드에 접속 되도록 상기 사전에 정하게 된 대응의 제2의 패드(PB1-PB16)에 접속되는 반도체 기억장치.
  8. 제1항에 있어서, 상기 제1의 변 방향에 따라 연재하고, 상기 복수의 제2의 패드의 사전에 정하게 된 대응의 패드(PS)과 접속되는 복수의 제1의 리드(Fb)와 상기 복수의 제1의 리드와 다른 층에 배치되어, 상기 제2의 변 방향에 따라 연장하고, 상기 복수의 제1의 패드(PL)의 사전에 정하게 된 대응의 패드와 접속되는 복수의 제2의 리드(Fa)를 더 구비하는 반도체 기억장치.
  9. 제1항에 있어서, 칩(1)은 십자형의 4부분으로 분할되고, 상기 반도체 메모리 장치는 상기 4부분에 배열되는 복수의 메모리 블록(MB1-MB4)을 더 구비하는 반도체 메모리 장치.
  10. 제9항에 있어서 상기 칩(1)은 4개의 동일 부분의 십자형으로 분할 되는 반도체 메모리 장치.
  11. 제9항에 있어서 상기 칩(1)은 상기 복수의 제1패드(PDa-PD1)의 선에 평행인 제1변(LS)과 상기 복수의 제2패드(DPa-DPg)의 선에 평행인 제2변(SS)을 가지고, 제1패드는 대응 메모리 블록에 대응하여 설치되며, 상기 제1변의 방향으로 대응하는 메모리 블록(MB1,MB3)의 중앙 부근에 설치되는 DQ 패드(DQ)를 포함하는 반도체 메모리 장치.
  12. 제9항에 있어서, 상기 칩(1)은 제1패드(DPa-DPp)의 선에 병행인 제1변(LS)과, 제2패드 (DPa-DPg)의 선에 병행인 제2변(SS)을 가지고, 제1패드는 대응하는 메모리 블록과 데이터 통신하기 위해, 각 메모리 블록 용 소정수의 복수의 DQ 패드 (DQ)를 포함하고, 소젓수의 DQ 패드는 제1변의 방향으로 대응하는 메모리 블록의 중앙에 대해 대칭으로 배열되는 반도체 메모리 장치.
  13. 제9항에 있어서, 십자형 영영(CHa-CHc)은 메모리 블록은 그위에 형성된 액세스 하는 것을 제어하는 주변회로(5a,5b)를 가지고, 제1패드의 라인과 제2패드의 라인 양쪽의 중앙부분에 위치하고 있는 반도체 메모리 장치.
  14. 제11항에 있어서, 상기 제1의 변(LS)은 상기 제2의 변(SS)보다 긴 반도체 메모리 장치.
  15. 제12항에 있어서, 상기 제1의 변(LS)은 상기 제2의 변(SS)보다 긴 반도체 메모리 장치.
  16. 제1의 변과 제2의 변을 가지는 구형 형상을 가지고, 그의 표면에 적어도 메모리셀의 어레이가 형성되는 반도체 칩(1)과 상기 제2의 변(3)방향에 대해 중앙부에 형성되는 상기 제1의 변 방향에 따라 연장하는 제1의 중앙영역(2)에 배치되는 장치 외부의 전기적 접속을 실현하기 위한 복수의 제1의 패드(PDA)와 상기 제1의 변의 양단부 각각에서, 상기 제2의 변에 따라 배치되는 장치 외부의 전기적 접속을 실현하기 위한 복수의 제2의 패드(PDBa,DPBab)를 구비하는 반도체 기억장치.
  17. 제16항에 있어서, 상기 칩(1)의 제1의 변(LS)에 배치되는 외부리드 단자에 대응하여 배치되고, 상기 칩 상에 걸쳐서 상기 제2의 변(SS) 방향에 연장하여 배치되어, 상기 복수의 제1패드(PDA)의 사정에 정하게 된 대응의 제1의 패드와 접속되는 복수의 제1의 리드(FLDA)와 상기 제2의 변에 따라 배치되는 외부 리드 단자에 대응하여 배치되고, 상기 복수의 제2의 패드(PDBa, DPBab)의 사전에 정하게 된 대응의 제2의 패드에 접속하는 복수의 제2의 리드(FDa, FDb)를 더 구비하는 반도체 기억장치.
  18. 제1의 변과 제2의 변(LS, SS)을 가지는 구형형상을 가지고 2의 표면에 적어도 메모리 셀의 어레이(MB1-MB4)가 형성되는 반도체 칩(1)과 상기 제1변의 양 단부에 상기 반도체 칩이 주변 영역(10a,10b) 반도체 칩 상에 상기 제1면의(LS)의 방향에 중앙영역(3)에서 상기 제2변(SS)의 방향에 배치된 장치 외부의 전기적 접속을 실현하기 위한 복수의 패드(PDBa-PDBc)를 구비하는 반도체 기억장치.
  19. 제18항에 있어서, 상기 제1의 변 방향에 따라 배치되는 외부 핀 단자에 연결 되고, 상기 중앙영역(3)의 패드(PDBC)의 서전에 정하게 된 대응의 패드를 접속하는 복수의 리드(FLDC)를 더 구비하는 반도체 기억장치.
  20. 상기 제1변과 수직한 제1변(SS) 및 제2변(LS)을 가지는 칩(1)상에 형성된 반도체 장치에 있어서, 제2변에 대해, 중앙부(3)에 제1변의 방향으로 조정되어 배열된 복수의 제1패드(PS : PDBC)와 상기 중앙부와 다른 부(2: 10a,10b)에 제1 및 제2변 중의 어느 하나의 방향으로 배열된 복수의 제2패드(PL : PDBa, PDBc)를 구비하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960013507A 1995-05-12 1996-04-29 점유면적의 저감된 패드배치를 가지는 반도체기억장치 및 그를 위한 패드배치방법 Expired - Fee Related KR100218875B1 (ko)

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