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KR960016690A - 1칩화상처리용디바이스 - Google Patents

1칩화상처리용디바이스 Download PDF

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Publication number
KR960016690A
KR960016690A KR1019950025089A KR19950025089A KR960016690A KR 960016690 A KR960016690 A KR 960016690A KR 1019950025089 A KR1019950025089 A KR 1019950025089A KR 19950025089 A KR19950025089 A KR 19950025089A KR 960016690 A KR960016690 A KR 960016690A
Authority
KR
South Korea
Prior art keywords
image processing
processing device
chip
storage unit
chip image
Prior art date
Application number
KR1019950025089A
Other languages
English (en)
Other versions
KR960006281B1 (ko
Inventor
도시히꼬 오구라
히로아끼 아오쓰
고오이찌 기무라
히로미찌 에노모드
다다시 교오다
Original Assignee
미다 가쓰시게
가부시기가이샤 히다찌세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP60105844A external-priority patent/JPH0697394B2/ja
Priority claimed from JP60105845A external-priority patent/JP2735173B2/ja
Application filed by 미다 가쓰시게, 가부시기가이샤 히다찌세이사꾸쇼 filed Critical 미다 가쓰시게
Application granted granted Critical
Publication of KR960006281B1 publication Critical patent/KR960006281B1/ko
Publication of KR960016690A publication Critical patent/KR960016690A/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/10—Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Input (AREA)
  • Dram (AREA)
  • Image Generation (AREA)
  • Read Only Memory (AREA)
  • Image Processing (AREA)
  • Logic Circuits (AREA)
  • Memory System (AREA)

Abstract

본 발명은 1칩화상처리용디바이스에 관한 것이며, 표시화면에 표시하기 위한 화상데이터를 격납하는 기억부와, 이 기억부로부터 독출된 화상데이터와 외부데이터와의 배타적 논리화(論理和)에 의한 논리연산을 실행하는 논리연산부를 칩내에 구비하여 이루어짐으로써, 게산시간의 단축을 도모할 수 있고, 액세스횟수의 삭감을 도모할 수 있으므로, 고속 그래픽디스플레이시스템의 구축이 가능하고, 또한 임의의 데이터폭으로 리드·모디화이·라이트 동작을 실행할 수 있다.

Description

1칩화상처리용디바이스
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 일실시예의 기억회로를 나타낸 블록도.

Claims (3)

  1. 표시화면에 표시하기 위한 화상데이터를 격납하는 기억부와, 이 기억부로부터 독출된 화상데이터와 외부데이터와의 배타적 논리화(論理和)에 의한 논리연산을 실행하는 논리연산부를 칩내에 구비하여 이루어지는 것을 특징으로 하는 1칩화상처리용디바이스.
  2. 제1항에 있어서, 화상처리시스템중에서, 상기 1칩화상처리디바이스의 출력은 표시장치에 접속되어 이루어지는 것을 특징으로 하는 1칩화상처리용디바이스.
  3. 제1항에 있어서, 화상처리시스템중에서, 상기 외부데이터는 마이크로프로세서로부터 공급되어 이루어지는 것을 특징으로 하는 1칩화상처리용디바이스.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950025089A 1985-05-20 1995-08-16 I칩화상처리용 디바이스 KR960006281B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP85-105844 1985-05-20
JP60105844A JPH0697394B2 (ja) 1985-05-20 1985-05-20 記憶回路
JP85-105845 1985-05-20
JP60105845A JP2735173B2 (ja) 1985-05-20 1985-05-20 ワンチップメモリデバイス
KR1019860003912A KR950014553B1 (ko) 1985-05-20 1986-05-20 논리기능을 가진 기억회로

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
KR1019860003912A Division KR950014553B1 (ko) 1985-05-20 1986-05-20 논리기능을 가진 기억회로

Publications (2)

Publication Number Publication Date
KR960006281B1 KR960006281B1 (ko) 1996-05-13
KR960016690A true KR960016690A (ko) 1996-05-22

Family

ID=26446070

Family Applications (6)

Application Number Title Priority Date Filing Date
KR1019860003912A KR950014553B1 (ko) 1985-05-20 1986-05-20 논리기능을 가진 기억회로
KR1019950025086A KR960006278B1 (ko) 1985-05-20 1995-08-16 데이터처리시스템
KR1019950025084A KR960006276B1 (ko) 1985-05-20 1995-08-16 메모리시스템
KR1019950025088A KR960006280B1 (ko) 1985-05-20 1995-08-16 1칩메모리 디바이스와 외부디바이스를 가지는 시스템
KR1019950025089A KR960006281B1 (ko) 1985-05-20 1995-08-16 I칩화상처리용 디바이스
KR1019950025085A KR960006277B1 (ko) 1985-05-20 1995-08-16 I칩메모리디바이스

Family Applications Before (4)

Application Number Title Priority Date Filing Date
KR1019860003912A KR950014553B1 (ko) 1985-05-20 1986-05-20 논리기능을 가진 기억회로
KR1019950025086A KR960006278B1 (ko) 1985-05-20 1995-08-16 데이터처리시스템
KR1019950025084A KR960006276B1 (ko) 1985-05-20 1995-08-16 메모리시스템
KR1019950025088A KR960006280B1 (ko) 1985-05-20 1995-08-16 1칩메모리 디바이스와 외부디바이스를 가지는 시스템

Family Applications After (1)

Application Number Title Priority Date Filing Date
KR1019950025085A KR960006277B1 (ko) 1985-05-20 1995-08-16 I칩메모리디바이스

Country Status (2)

Country Link
US (1) US5113487A (ko)
KR (6) KR950014553B1 (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69129401T2 (de) * 1990-12-25 1998-10-29 Mitsubishi Electric Corp Halbleiterspeichervorrichtung mit einem grossen Speicher und einem Hochgeschwindigkeitsspeicher
JP3321651B2 (ja) * 1991-07-26 2002-09-03 サン・マイクロシステムズ・インコーポレーテッド コンピュータの出力表示のためのフレームバッファメモリを提供する装置および方法
EP0681279B1 (en) 1994-05-03 2001-07-18 Sun Microsystems, Inc. Frame buffer random access memory and system
KR102364506B1 (ko) * 2020-09-01 2022-02-18 금호타이어 주식회사 벨트 지지 고무를 구비한 공기입타이어

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5438724A (en) * 1977-09-02 1979-03-23 Hitachi Ltd Display unit
JPS58209784A (ja) * 1982-05-31 1983-12-06 株式会社東芝 メモリシステム
US4435792A (en) * 1982-06-30 1984-03-06 Sun Microsystems, Inc. Raster memory manipulation apparatus
JPS5960658A (ja) * 1982-09-30 1984-04-06 Fujitsu Ltd 論理機能を備えた半導体記憶装置
JPS5979293A (ja) * 1982-10-29 1984-05-08 株式会社東芝 表示装置
JPS59216249A (ja) * 1983-05-23 1984-12-06 Toshiba Corp 集積回路装置
US4742474A (en) * 1985-04-05 1988-05-03 Tektronix, Inc. Variable access frame buffer memory

Also Published As

Publication number Publication date
KR960006281B1 (ko) 1996-05-13
KR960006276B1 (ko) 1996-05-13
KR860009421A (ko) 1986-12-22
KR960016686A (ko) 1996-05-22
KR960006277B1 (ko) 1996-05-13
KR960016689A (ko) 1996-05-22
KR960006280B1 (ko) 1996-05-13
KR960016685A (ko) 1996-05-22
KR960006278B1 (ko) 1996-05-13
KR950014553B1 (ko) 1995-12-05
KR960016687A (ko) 1996-05-22
US5113487A (en) 1992-05-12

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