KR960012574B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- KR960012574B1 KR960012574B1 KR1019930000488A KR930000488A KR960012574B1 KR 960012574 B1 KR960012574 B1 KR 960012574B1 KR 1019930000488 A KR1019930000488 A KR 1019930000488A KR 930000488 A KR930000488 A KR 930000488A KR 960012574 B1 KR960012574 B1 KR 960012574B1
- Authority
- KR
- South Korea
- Prior art keywords
- film
- polysilicon film
- semiconductor device
- polysilicon
- manufacturing
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 39
- 229920005591 polysilicon Polymers 0.000 claims abstract description 39
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 25
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
제 1 도 내지 제 4 도는 종래 반도체장치의 콘택플러그 형성방법을 제조공정의 순서에 따라 그 단면을 도시하고 있으며,1 through 4 illustrate cross-sectional views of a conventional method for forming a contact plug in a semiconductor device according to a manufacturing process.
제 5 도 내지 제 8 도는 본 발명의 반도체장치의 콘택플러그 형성방법을 제조공정에 따라 순서대로 단면을 도시하고 있다.5 through 8 illustrate cross-sectional views of a method for forming a contact plug of a semiconductor device of the present invention in order according to a manufacturing process.
본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 콘택홀(Contact Hole)내에 폴리실리콘(Polysilicon)을 이용한 콘택플러그(Contact Plug)를 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a contact plug using polysilicon in a contact hole.
반도체장치의 고집적화로 설계치수가 써브미크론(submicron) 이하로 미세화됨에 따라 트랜지스터의 면적이 감소하고, 트랜지스터의 소오스(Source) 및 드레인(Drain)영역에 형성하는 콘택홀이 작아져 콘택홀이 큰 종횡비(aspect ratio)를 갖게 되면서 사진공정 과정에서 미세한 미스얼라인(Misalign)에 의해서도 게이트(Gate)전극과 비트라인(Bit Line) 또는 스토리지(Storage)전극 사이의 접촉에 의한 소자파괴가 발생되어 우수한 단차피복성(Stepcoverage)을 갖는 콘택플러그가 요구되었다. 이러한 문제점을 해결하기 위하여 종래에는 게이트전극 상부와 측면에 고온산화막을 형성한 상태에서 폴리실리콘과 같은 도전성 물질로 플러그를 형성하고, 그 위에 콘택홀을 형성하여 스토리지전극과 비트라인을 형성하는 방법이 알려져 있다. 이와같은 종래 기술의 하나가 첨부도면 제 1 도 내지 제 4 도에 도시되어 있으며, 이를 참조하여 종래 반도체장치의 콘택플러그 형성방법을 알아보기로 한다.As the design dimension becomes smaller than submicron due to the high integration of semiconductor devices, the area of the transistor decreases, and the contact hole formed in the source and drain regions of the transistor is small, so that the contact hole has a large aspect ratio. (aspect ratio) and excellent misalignment due to device destruction caused by contact between gate electrode and bit line or storage electrode even by minute misalignment during photo process There was a need for a contact plug with a step coverage. In order to solve this problem, a method of forming a storage electrode and a bit line by forming a plug with a conductive material such as polysilicon in a state where a high temperature oxide film is formed on upper and side surfaces of a gate electrode, and forming a contact hole thereon Known. One such prior art is shown in FIGS. 1 through 4, and a method of forming a contact plug of a conventional semiconductor device will be described with reference to the drawings.
먼저, 반도체장치(11)에 통상의 방법으로 게이트전극(13)을 형성하고, 상기 게이트전극(13)의 상부와 측면에 고온산화막(14)을 형성한 다음, 소자의 드레인 또는 소오스로 이용될 확산층(12)을 형성하고, 계속해서 상기 구조물의 기판 전면상에 폴리실리콘막(15)을 약 5000Å 정도의 두께로 침적시킨다(제 1 도). 그 다음, 상기 폴리실리콘막(15)상에 질화막(16)을 형성하고, 그 위에 감광막을 도포한 후, 사진공정으로 게이트전극 상단의 상기 감광막을 패터닝하여 감광막패턴(17)을 형성한다(제 2 도). 이어서, 상기 감광막패턴(17)을 식각마스크로 하고 식각공정을 통하여 질화막패턴(16A)을 형성한 다음, 상기 감광막패턴(17)을 제거한 후, 상기 폴리실리콘막(15)을 산화시켜 소오스나 드레인영역 위의 폴리실리콘막(15)을 선택적으로 산화하여 산화막(18)을 형성시킨다(제 3 도). 이어서 상기 질화막패턴을 제거한 다음, 상기 산화막(18)을 식각저지층으로 하여 폴리실리콘막(15)을 건식식각하면 소오스나 드레인영역으로 이용될 확산층(12) 위에 폴리실리콘플러그(19)나 형성된다(제 4 도).First, the gate electrode 13 is formed in the semiconductor device 11 by a conventional method, and the high temperature oxide film 14 is formed on the top and side surfaces of the gate electrode 13, and then used as a drain or a source of the device. The diffusion layer 12 is formed, and then the polysilicon film 15 is deposited to a thickness of about 5000 kPa on the entire surface of the substrate of the structure (FIG. 1). Next, a nitride film 16 is formed on the polysilicon film 15, a photoresist film is applied thereon, and then the photoresist film on the top of the gate electrode is patterned by a photolithography process to form a photoresist pattern 17 2 degrees). Subsequently, the photoresist layer pattern 17 is used as an etch mask, and a nitride layer pattern 16A is formed through an etching process. After the photoresist layer pattern 17 is removed, the polysilicon layer 15 is oxidized to form a source or drain. The polysilicon film 15 on the region is selectively oxidized to form an oxide film 18 (FIG. 3). Subsequently, after removing the nitride layer pattern, dry etching the polysilicon layer 15 using the oxide layer 18 as an etch stop layer forms a polysilicon plug 19 on the diffusion layer 12 to be used as a source or a drain region. (Figure 4).
그러나, 상기 질화막패턴을 형성하기 위한 사진식각공정에서 미스얼라인이 발생하면 실리콘산화막을 식각저지층으로 하여 폴리실리콘막을 식각하는 과정에서 확산층 위의 폴리실리콘층에 피팅(Pitting)이 유발할 수 있으며, 또한 사진공정을 거쳐야 하므로 공정이 복잡해지는 문제가 있다.However, if a misalignment occurs in the photolithography process for forming the nitride film pattern, a fitting may be caused to the polysilicon layer on the diffusion layer in the process of etching the polysilicon film using the silicon oxide film as an etch stop layer. In addition, there is a problem that the process is complicated because it must go through a photo process.
따라서 본 발명에서는 SOG(Spin on Glass)막을 폴리실리콘막의 식각저지층으로 사용하여 실리콘의 피팅 현상을 방지하고, 사진공정을 배제하여 제조공정을 단순화하는 데에 그 목적이 있다.Therefore, an object of the present invention is to use a spin on glass (SOG) film as an etch stop layer of a polysilicon film to prevent the fitting phenomenon of silicon and to simplify the manufacturing process by excluding the photo process.
상기한 목적을 달성하기 위한 본 발명의 바람직한 일실시예는 반도체기판에 게이트전극과 상기 게이트전극의 상부와 측면에 고온산화막(HTO)을 형성하고, 소자의 활성영역인 확산층이 형성된 반도체장치에 콘택플러그를 형성하는 방법에 있어서, 상기 구조물의 기판 전면에 폴리실리콘막을 침적하는 공정 ; SOG막을 도포하는 공정 ; SOG막을 에치백하여 불순물영역 위에 식각저지층을 형성하는 공정; 폴리실리콘막을 식각하는 공정을 구비하여 이루어진 것을 특징으로 한다.A preferred embodiment of the present invention for achieving the above object is to form a gate electrode and a high temperature oxide film (HTO) on the upper side and the side of the gate electrode on the semiconductor substrate, and contacts the semiconductor device having a diffusion layer formed as an active region of the device A method of forming a plug, the method comprising: depositing a polysilicon film on an entire surface of a substrate of the structure; Applying a SOG film; Etching back the SOG film to form an etch stop layer over the impurity region; And a step of etching the polysilicon film.
상기 폴리실리콘막의 두께는 500Å-1500Å 정도의 두께로 형성하고, 상기 SOG막의 두께는 4000Å-6000Å 정도의 두께로 형성하는 것이 바람직하다.The thickness of the polysilicon film is preferably formed to a thickness of about 500 kPa-1500 kPa, and the thickness of the SOG film is preferably formed to a thickness of about 4000 kPa-6000 kPa.
또한, 상기 폴리실리콘막 식각공정후에 불순물영역상에 잔류하는 폴리실리콘막 위에 선택적으로 폴리실리콘막을 성장시키는 방법을 통해 제 2 폴리실리콘막을 침적하는 공정이 추가될 수도 있다. 이때, 상기 제 2 폴리실리콘막의 성장두께는 상기 게이트전극의 폭에 대해 약 1/4-1/2 정도의 두께가 되도록 하는 것이 바람직하다.In addition, after the polysilicon film etching process, a process of depositing a second polysilicon film may be added by selectively growing a polysilicon film on the polysilicon film remaining on the impurity region. In this case, it is preferable that the growth thickness of the second polysilicon film is about 1 / 4-1 / 2 of the width of the gate electrode.
상기한 본 발명에 의하면 통상의 SOG막 특성을 이용하여 게이트전극 사이의 활성영역위에 SOG막으로 이루어진 식각저지층을 미스얼라인 없이 자기정합적으로 형성시킬 수가 있다.According to the present invention described above, the etching stop layer made of the SOG film can be self-aligned without misalignment on the active region between the gate electrodes by using the conventional SOG film characteristics.
이하, 첨부도면을 참조하여 본 발명을 더욱 상세히 설명하기로 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
첨부도면 제 5 도 내지 제 8 도는 본 발명의 반도체장치의 콘택플러그 형성방법을 제조공정에 따라 순서대로 단면을 도시하고 있다.5 through 8 illustrate cross-sectional views of a method for forming a contact plug of a semiconductor device of the present invention in order according to a manufacturing process.
먼저, 반도체기판(21)에 통상의 방법으로 게이트전극(23)을 형성하고, 상기 게이트전극(23)의 상부와 측면에 고온산화막(24)을 약 2000Å-4000Å 정도의 두께로 형성한 다음, 소자의 드레인 또는 소오스로 이용될 확산층(22)을 형성하고, 계속해서 상기 구조물의 기판 전면상에 폴리실리콘막(25)을 약 500Å-1500Å 정도의 두께로 침적시킨 다음, 상기 폴리실리콘막(25)상에 SOG막(26)을 약 4000Å-6000Å 정도의 두께로 도포한다(제 5 도). 이어서, 게이트전극(23) 상부의 폴리실리콘막(25)이 노출될때까지 상기 SOG막(26)을 에치백(Etch Back)하면 게이트전극(23) 사이의 확산층(22)위에 SOG막으로 이루어진 식각저지층(27)을 미스얼라인 없이 자기정합적으로 형성시킬 수가 있고(제 6 도), 상기 확산영역 상부에 잔류하는 SOG막(27)을 식각저지층으로 하고, 상기 게이트전극(23) 상부에 노출된 폴리실리콘막(25)을 식각한 다음, 상기 SOG막으로 이루어진 식각저지층(27)을 제거하면 상기 활성층(22)상에 폴리실리콘막으로 이루어진 콘택플러그(28)가 형성된다(제 7 도). 그 다음, 상기 콘택플러그(28)상에 비트라인 또는 스토리지전극의 전기적 콘택을 위한 콘택홀 형성시, 공정의 용이성을 위하여 선택적 폴리실리콘 성장 공정을 진행하여 제 2 폴리실리콘(29)을 성장시킨다(제 8 도).First, the gate electrode 23 is formed on the semiconductor substrate 21 by a conventional method, and the high temperature oxide film 24 is formed on the top and side surfaces of the gate electrode 23 to a thickness of about 2000 kPa to 4000 kPa. A diffusion layer 22 to be used as a drain or source of the device is formed, and then a polysilicon film 25 is deposited to a thickness of about 500 kV to 1500 kC on the entire surface of the substrate of the structure, and then the polysilicon film 25 Is applied to a thickness of about 4000 kPa to 6000 kPa (FIG. 5). Subsequently, when the SOG film 26 is etched back until the polysilicon film 25 on the gate electrode 23 is exposed, the SOG film is etched on the diffusion layer 22 between the gate electrodes 23. The stop layer 27 can be formed self-aligning without misalignment (FIG. 6), and the SOG film 27 remaining on the diffusion region is used as an etch stop layer, and the top of the gate electrode 23 is formed. After etching the polysilicon film 25 exposed to the substrate, the etch stop layer 27 made of the SOG film is removed to form a contact plug 28 formed of a polysilicon film on the active layer 22 (the 7 degrees). Then, when forming a contact hole for electrical contact of the bit line or the storage electrode on the contact plug 28, the second polysilicon 29 is grown by performing a selective polysilicon growth process for ease of processing ( 8).
따라서 상기한 본 발명의 방법에 의하면 폴리실리콘막의 식각저지층으로 자기정합적으로 형성된 SOG막을 사용하여 실리콘의 피팅현상을 방지하고, 사진공정을 배제하여 제조공정이 단순화되어 반도체장치의 전기적특성 및 제조수율을 크게 향상시키는 잇점이 있다.Therefore, according to the method of the present invention described above, the SOG film formed as an etch stop layer of the polysilicon film is used to prevent the fitting phenomenon of the silicon, and the manufacturing process is simplified by excluding the photo process, thereby simplifying the electrical characteristics and manufacturing of the semiconductor device. This has the advantage of greatly improving the yield.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930000488A KR960012574B1 (en) | 1993-01-15 | 1993-01-15 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930000488A KR960012574B1 (en) | 1993-01-15 | 1993-01-15 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940018913A KR940018913A (en) | 1994-08-19 |
| KR960012574B1 true KR960012574B1 (en) | 1996-09-23 |
Family
ID=19349683
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930000488A KR960012574B1 (en) | 1993-01-15 | 1993-01-15 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR960012574B1 (en) |
-
1993
- 1993-01-15 KR KR1019930000488A patent/KR960012574B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR940018913A (en) | 1994-08-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4295924A (en) | Method for providing self-aligned conductor in a V-groove device | |
| KR100278273B1 (en) | A method for forming contact holes in semiconductor device | |
| KR100223832B1 (en) | Semiconductor device and manufacturing method | |
| US5874330A (en) | Method for fabricating semiconductor device | |
| KR100226749B1 (en) | Manufacturing Method of Semiconductor Device | |
| KR100226761B1 (en) | Method for semiconductor device fabrication | |
| KR960012574B1 (en) | Manufacturing method of semiconductor device | |
| KR0141197B1 (en) | Method of contact hole in semiconductor device | |
| KR100291823B1 (en) | Manufacturing method of semiconductor device | |
| KR100390891B1 (en) | Manufacturing method of highly integrated semiconductor device | |
| KR100307541B1 (en) | Manufacturing method for mos transistor | |
| KR100198637B1 (en) | Method of manufacturing semiconductor device | |
| KR20010008839A (en) | Method of forming self-aligned contacts in semiconductor device | |
| KR100215871B1 (en) | Method for fabricating semiconductor device | |
| KR0126641B1 (en) | Manufacturing method of semiconductor device | |
| KR0172832B1 (en) | Semiconductor device manufacturing method | |
| KR0147770B1 (en) | Manufacture method of semiconductor device | |
| KR0129585B1 (en) | Fabrication method of transistor | |
| KR940011736B1 (en) | Manufacturing method of semiconductor device | |
| KR100223333B1 (en) | Method for forming a contact of semiconductor device | |
| KR100338095B1 (en) | Contact hole formation method of semiconductor device | |
| KR100237758B1 (en) | Manufacture of semiconductor device | |
| KR100200309B1 (en) | Method of manufacturing semiconductor device | |
| KR100244261B1 (en) | Plug forming method in semiconductor device | |
| KR100280534B1 (en) | MOS transistor manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19930115 |
|
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19930115 Comment text: Request for Examination of Application |
|
| PG1501 | Laying open of application | ||
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 19960425 Patent event code: PE09021S01D |
|
| G160 | Decision to publish patent application | ||
| PG1605 | Publication of application before grant of patent |
Comment text: Decision on Publication of Application Patent event code: PG16051S01I Patent event date: 19960828 |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19961210 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 19970114 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 19970114 End annual number: 3 Start annual number: 1 |
|
| PR1001 | Payment of annual fee |
Payment date: 19990814 Start annual number: 4 End annual number: 4 |
|
| PR1001 | Payment of annual fee |
Payment date: 20000814 Start annual number: 5 End annual number: 5 |
|
| PR1001 | Payment of annual fee |
Payment date: 20010807 Start annual number: 6 End annual number: 6 |
|
| PR1001 | Payment of annual fee |
Payment date: 20020807 Start annual number: 7 End annual number: 7 |
|
| PR1001 | Payment of annual fee |
Payment date: 20030808 Start annual number: 8 End annual number: 8 |
|
| PR1001 | Payment of annual fee |
Payment date: 20040331 Start annual number: 9 End annual number: 9 |
|
| FPAY | Annual fee payment |
Payment date: 20050802 Year of fee payment: 10 |
|
| PR1001 | Payment of annual fee |
Payment date: 20050802 Start annual number: 10 End annual number: 10 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |