KR940011736B1 - Manufacturing method of semiconductor device - Google Patents

Abstract

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Description

Manufacturing Method of Semiconductor Device

1 is a conventional cross-sectional view.

2 is a manufacturing process diagram according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a contact hole in a cell by using self-alignment and planarizing a lower layer of a bit line.

As semiconductor memory cells are highly integrated, contact holes in cells are required to be smaller in size. In addition, planarization of the bit line underlying layer is required for a bit line stringer-free process. However, when the lower layer of the bit line is planarized, the self-aligning process of the buried contact cannot be performed.

FIG. 1 (a) and FIG. 1 (d) are manufacturing process diagrams showing a conventional contact hole forming method.

A gate electrode 16 having a gate insulating film 14 as an intermediate layer is formed on the first conductive semiconductor substrate 10 on which the field oxide film 12 is formed in FIG. 1 (a), and the gate electrode 16 is formed. The spacer 18 is formed on the side wall. Then, an oxide film 20 for self matching contact is formed on the upper surface of the substrate. In FIG. 1 (b), a direct contact hole and a buried contact hole are formed in a self-aligning manner, and then a pad polycrystalline silicon layer 22 is formed on the substrate 10. . The photolithography process is performed in FIG. 1C to form the pad polycrystalline silicon pattern 24 in each contact region. When the pad polycrystalline silicon pattern is formed in the direct contact and the buried contact, respectively, the size of the semiconductor memory device, which is becoming finer, is limited by the limitation of the photolithography process. Accordingly, it is common to form the pad polycrystalline silicon pattern on only one side.

In FIG. 1 (d), an insulating film 26 is formed on the upper surface of the substrate 10, and then a planarization process is performed.

Then, the insulating layer 26 in a predetermined region is etched to form a contact hole.

As can be seen from the above description, there is a problem in that the insulating film must be deeply etched when forming contact holes.

In addition, since the contact hole is formed on the upper surface after the pad polycrystalline silicon pattern having a predetermined area is formed, accurate alignment is required, thereby reducing the process margin.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of forming a contact hole with a minimum etching depth when forming a contact hole in a method of manufacturing a semiconductor device.

In order to achieve the object of the present invention as described above, the direct contact hole and the buried contact hole are formed on the upper surface of the semiconductor substrate on which the field oxide film and the gate are formed, and then a conductive layer of first polycrystalline silicon is formed on the upper surface of the substrate. And then remove the insulator on the top surface of the substrate and then remove the first polycrystalline silicon between the direct and buried contact holes.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 (a) and 2 (b) is a manufacturing process diagram showing a contact hole forming method according to an embodiment of the present invention.

The gate oxide film 44 is formed as an intermediate layer on the first conductive semiconductor substrate 40 on which the field oxide film 42 is formed in FIG. 2 (a), and the gate surrounded by the oxide film and the sidewall spacers 48 on the upper surface thereof. An electrode 46 is formed. Then, an oxide film 50 for self-aligned contact is formed on the upper surface of the substrate 40.

In FIG. 2B, the substrates corresponding to the direct contact region and the buried contact region are exposed by forming the oxide layer pattern 52 for self-alignment contact in a self-aligning manner.

Next, a first polycrystalline silicon layer 54 is formed on the entire surface of the substrate 40.

In FIG. 2 (c), the insulating film 56 is applied to the entire surface of the substrate 40 to be planarized, and then directly applied until the surface of the first polycrystalline silicon layer 54 is exposed using a photo mask. The insulating layer 56 in the contact region and the buried contact region is etched to form an opening.

In FIG. 2 (d), the inside of the opening is filled with polycrystalline silicon to form a plug 58 made of polycrystalline silicon.

In FIG. 2E, the insulating layer 56 is removed by wet etching.

Next, in FIG. 2 (f), the exposed first polycrystalline silicon layer 54 is etched using the plug 58 as a mask. At this time, the plug is also etched by a predetermined thickness.

As a result, even if the upper surface of the substrate is planarized with an insulating material in the subsequent process, the etching payback for forming the contact hole is greatly reduced.

It is also possible to form contact areas in self-alignment, which increases the margin for misalignment.

3 (a) and 3 (b) are manufacturing process diagrams showing a contact hole forming method according to another embodiment of the present invention. The same numbers are used for the same names as in the second drawing.

In FIG. 3 (a), a polycrystalline silicon spacer 62 is formed on the sidewall of the plug 58 made of polycrystalline silicon.

In FIG. 3B, the exposed first polycrystalline silicon layer 54 is etched using the plug 58 and the spacer 62 as a mask.

At this time, the plug and spacer are also etched by a predetermined thickness.

In the above embodiment, the mask is formed of polycrystalline silicon, but in another embodiment of the present invention, the mask may be an oxide film or a nitride film.

By forming the spacer as described above, the pattern width of the first polycrystalline silicon layer is increased by the thickness of the spacer, so that a misalignment margin can be secured at the time of forming the contact hole.

As described above, in the method of manufacturing a semiconductor device, a polycrystalline silicon layer in contact with a direct contact region and an buried contact region is formed on a front surface of a substrate, and then polycrystalline is formed on the direct contact region and the buried contact region with a predetermined mask pattern. Since the first polycrystalline silicon layer is etched using the silicon plug as a mask, the etching depth can be greatly reduced in the subsequent process of forming contact holes. Accordingly, the step coverage of the bit line can be greatly improved.

In addition, the lower surface of the plug is used as the contact hole area, which increases the margin of the process when forming the contact hole.

Claims (5)

A method of manufacturing a semiconductor device in which a contact hole is formed on a first conductive semiconductor substrate having a field oxide film and a switching transistor, the method comprising: forming a first insulating film on the substrate, and then forming a substrate between the gates out of the transistor; A first step of forming a first contact hole by etching the first insulating film to expose the first insulating film, a second step of forming a first conductive layer and a second insulating film on the upper surface of the substrate, and then planarizing the surface of the substrate; A third step of forming a conductive plug by filling the conductive material between the remaining second insulating films after leaving the second insulating film in a region corresponding to the upper portion of the first insulating film remaining in the first step; and the remaining second A fourth step of removing the insulating film and a fifth step of simultaneously etching the exposed first conductive layer and the conductive plug having a predetermined thickness using the plug as a mask; A method for manufacturing a semiconductor device characterized in that the sixth step is constituted by any order of the first until the first conductive layer surface is exposed to form a second number of contact by etching to the conductive plugs of a predetermined area. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a spacer on the side wall of the plug after the fourth step. The method of claim 1, wherein the first conductive layer and the conductive material are polycrystalline silicon. The method of manufacturing a semiconductor device according to claim 1, wherein said first step is a self-aligning step. The method of claim 1, wherein the spacer is formed of polycrystalline silicon, an oxide film, or a nitride film.