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KR940018913A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR940018913A
KR940018913A KR1019930000488A KR930000488A KR940018913A KR 940018913 A KR940018913 A KR 940018913A KR 1019930000488 A KR1019930000488 A KR 1019930000488A KR 930000488 A KR930000488 A KR 930000488A KR 940018913 A KR940018913 A KR 940018913A
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KR
South Korea
Prior art keywords
polysilicon film
film
semiconductor device
manufacturing
polysilicon
Prior art date
Application number
KR1019930000488A
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Korean (ko)
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KR960012574B1 (en
Inventor
신유균
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019930000488A priority Critical patent/KR960012574B1/en
Publication of KR940018913A publication Critical patent/KR940018913A/en
Application granted granted Critical
Publication of KR960012574B1 publication Critical patent/KR960012574B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체장치의 제조방법에 관한 것으로, 특히 반도체기판에 게이트전극과 상기 게이트전극의 상부와 측면에 고온열산화막을 형성하고, 소자의 활성영역인 확산층이 형성된 반도체장치에 콘택플러그를 형성하는 방법에 있어서, 상기 구조물의 기판 전면에 폴리실리콘막을 증착하는 공정; SOG막을 도포하는 공저; SOG막을 에치백하여 활성영역 위에 식각저지층을 형성하는 공정; 폴리실리콘막을 식각하는 공정을 구비하여 이루어진 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a high temperature thermal oxide film is formed on a semiconductor substrate, and a contact plug is formed on a semiconductor device having a diffusion layer as an active region of the device. A method, comprising: depositing a polysilicon film over a substrate surface of the structure; A joint for applying an SOG film; Etching back the SOG film to form an etch stop layer over the active region; And a step of etching the polysilicon film.

따라서 상기한 본 발명의 방법에 의하면 폴리실리콘막의 식각저지층으로 자기정합적으로 형성된 SOG막을 사용하여 실리콘의 피팅현상을 방지하고, 사진공정을 배제하여 제조공정이 단순화되어 반도체장치의 전기적 특성 및 제조수율을 크게 향상시키는 잇점이 있다.Therefore, according to the method of the present invention described above, the SOG film formed as an etch stop layer of the polysilicon film is used to prevent the fitting phenomenon of the silicon, and the manufacturing process is simplified by excluding the photo process, thereby simplifying the electrical characteristics and manufacturing of the semiconductor device. This has the advantage of greatly improving the yield.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도 내지 제8도는 본 발명의 반도체장치의 콘택플로그 형성방법을 제조공정에 따라 순서대로 단면을 도시하고 있다.5 through 8 illustrate cross-sectional views of a method of forming a contact plug in a semiconductor device of the present invention in order according to a manufacturing process.

Claims (6)

반도체기판에 게이트전극과 상기 게이트전극의 상부와 측면에 고온산화막을 형성하고, 소자의 소오스/드레인영역으로 활용될 확산층이 형성된 반도체장치의 상기 확산층 상에 콘택플러그를 형성하는 방법에 있어서, 상기 구조물이 기판 전면에 폴리실리콘막을 침적하는 공정; SOG막을 도포하는 공정; 상기 SOG막을 에치백하여 상기 폴리실리콘막을 노출시키고 상기 확산층위에 식각저지층을 형성하는 공정; 상기 노출된 폴리실리콘막을 식각하는 공정을 구비하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.A method of forming a contact plug on a diffusion layer of a semiconductor device in which a high-temperature oxide film is formed on a semiconductor substrate, and a high-temperature oxide film is formed on upper and side surfaces of the gate electrode, and a diffusion layer to be used as a source / drain region of the device is formed. Depositing a polysilicon film on the entire surface of the substrate; Applying a SOG film; Etching back the SOG film to expose the polysilicon film and to form an etch stop layer on the diffusion layer; And etching the exposed polysilicon film. 제1항에 있어서, 상기 폴리실리콘막의 두께는 500Å - 1500Å 정도의 얇은두께로 형성하는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the polysilicon film has a thickness of about 500 kV-1500 kPa. 제3항에 있어서, 상기 SOG막의 두께는 4000Å - 6000Å 정도의 두께로 형성되는 것을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 3, wherein the SOG film has a thickness of about 4000 kPa-6000 kPa. 제1항에 있어서, 상기 SOG막을 에치백하여 활성영역 위에 식각저지층을 형성시킨다음, 상기 폴리실리콘막을 식각하고, 상기 폴리실리콘막 상에 추가로 제2폴리실리콘막을 형성시키는 공정을 구비하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 1, wherein the SOG film is etched back to form an etch stop layer over the active region, and then the polysilicon film is etched and a second polysilicon film is further formed on the polysilicon film. A method of manufacturing a semiconductor device, characterized in that. 제4항에 있어서, 상기 제2폴리실리콘막은 상기 폴리실리콘막상에 선택적 폴리실리콘 성장법을 이용하여 형성되는 것을 특징으로 하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 4, wherein the second polysilicon film is formed on the polysilicon film using a selective polysilicon growth method. 제5항에 있어서, 상기 제2폴리실리콘막의 성장두께는 상기 게이트전극의 폭에 대해 약 1/4-1/2정도의 두께가 되도록하는 것을 특징으로 하는 반도체장치의 제조방법.6. The method of claim 5, wherein the growth thickness of the second polysilicon film is about 1 / 4-1 / 2 of the width of the gate electrode. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930000488A 1993-01-15 1993-01-15 Manufacturing method of semiconductor device KR960012574B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930000488A KR960012574B1 (en) 1993-01-15 1993-01-15 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930000488A KR960012574B1 (en) 1993-01-15 1993-01-15 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR940018913A true KR940018913A (en) 1994-08-19
KR960012574B1 KR960012574B1 (en) 1996-09-23

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930000488A KR960012574B1 (en) 1993-01-15 1993-01-15 Manufacturing method of semiconductor device

Country Status (1)

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Also Published As

Publication number Publication date
KR960012574B1 (en) 1996-09-23

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