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KR950021525A - 얕은 접합의 소오스/드레인 영역과 실리사이드를 갖는 모스트랜지스터의 제조방법 - Google Patents

얕은 접합의 소오스/드레인 영역과 실리사이드를 갖는 모스트랜지스터의 제조방법 Download PDF

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Publication number
KR950021525A
KR950021525A KR1019930028018A KR930028018A KR950021525A KR 950021525 A KR950021525 A KR 950021525A KR 1019930028018 A KR1019930028018 A KR 1019930028018A KR 930028018 A KR930028018 A KR 930028018A KR 950021525 A KR950021525 A KR 950021525A
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KR
South Korea
Prior art keywords
film
titanium nitride
nitride film
gate
titanium
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KR1019930028018A
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English (en)
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KR0135163B1 (ko
Inventor
변정수
김재정
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019930028018A priority Critical patent/KR0135163B1/ko
Priority to US08/190,664 priority patent/US5607884A/en
Priority to DE4406849A priority patent/DE4406849C2/de
Priority to JP6163338A priority patent/JP2819240B2/ja
Publication of KR950021525A publication Critical patent/KR950021525A/ko
Application granted granted Critical
Publication of KR0135163B1 publication Critical patent/KR0135163B1/ko

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 타타늄질화막이 열처리시 상분리되는 현상을 이용함으로써, 한번의 옅처리 공정으로 박막의 타타늄 실리사이드를 형성시킬 수 있을 뿐만아니라 상용 이온 주입장치를 이용하여 얕은 접합의 소오스/드레인영역을 형성시킬 수 있는 모스 트랜지스터의 제조방법으로서, 실리콘기판상에 필드산화공정을 수행하여 소자 분리용 필드산화막을 형성하는 스텝과, 실리콘기판상에 게이트 절연막과 폴리 실리콘막으로 된 게이트를 형성하는 스텝과, 게이트의 측벽에 스페이서를 형성하는 스텝과, 기판 전면에 티타늄과잉의 티타늄 질화막을 증착시키는 스텝과, 열처리 공정을 수행하여 타타늄 질화막과 게이트 계면과 실리콘기판과 티타늄 질화막의 계면에 티타늄 실리 사이드막을 형 성하고, 필드 산화막 및 측벽 스페이서와 티타늄 질화막의 계면에 TixNyOz막을 형성하는 스텝과, 기판 전면에 도판트를 이온 주입하는 스텝과, 열처리 공정을 수행하여 티타늄 실리사이드막내에 이온 주입된 도판트를 실리콘기판으로 확산시켜 얕은 접합의 소오스/드레인영역을 형성하는 스텝과 티타늄 실리사이드막을 제외한 비반응 티타늄질화막과 반응된 TixNy0z막을 NH,OH/H202용액으로 선택적으로 제거하는 스텝을 포함한다.

Description

얕은 접합의 소오스/드레인 영역과 실리사이드를 갖는 모스트랜지스터의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도 (A)- (E)는 본 발명의 SADS 공정을 이용한 모스 트랜지스터의 제조공정도.

Claims (7)

  1. 실리콘기판 (41)상에 필드산화공정을 수행하여 필드산화막 (42)을 형성하는 스텝과, 실리콘기판 (41)상에 박막의 절연막과 폴리 실리콘막을 증착시키고 패터닝하여 게이트 절연막 (43)과 게이트 (44)를 형성하고, 게이트 (44)가 형성된 부분을 제외한 실리콘기판(41)을 노출시키는 스텝과, 게이트(44)의 측벽에 산화막으로된 스페이서 (45)를 형성하는 스텝과, 기판 전면에 걸쳐 티타늄질화막 (46)을 증착시키는 스텝과, 급속 열처리공정을 수행하여 노출된 실리콘기관(41)과 티타늄질화막(46)의 계면과 게이트(44)와 티타늄질화막(46)의 계면에 티타늄실리사이드막 (47, 49)을 형성하고, 필드산화막 (42) 및 측벽스페이서 (45)와 티타늄질화막 (46)의 계면에 TixNyOz막(48)을 형성하는 스텝과, 기판 전면에 걸쳐 기판과 반대 도전형을 갖는 불순물을 이온 주입하는 스텝과, 열처리공정을 수행하여 티타늄실리사이드막(47)내에 이온주입된 불순물을 기판(41)으로 확산시켜 얕은 접합의 소오스/드레인 영역 (50)을 형성하는 스텝과, 티타늄실리사이드막(48, 49)을 제외한 남아있는 티타늄질화막(46)과 TixNyOz막 (48)을 선택적으로 제거하는 스텝을 포함하는 것을 특징으로 하는 얕은 접합의 소오스/드레인영역과 실리사이드를 갖는 모스 트랜지스터의 제조방법.
  2. 제1항에 있어서, 타타늄 질화막(46)은 티타늄 과잉의 티타늄질화막(TiNx) (0〈x〈1)인 것을 특징으로 하는 얕은 접합의 소오스/드레인영역과 실리사이드를 갖는 모스 트랜지스터의 제조방법.
  3. 제1항에 있어서, 티타늄질화막 (46)은 반응성 스퍼터링법으로 증착시키는 것을 특징으로 하는 모스 트랜지스터의 제조방법.
  4. 제 1항에 있어서, 급속 열처리 공정을 800℃ 정도의 고온에서 수행하는 것을 특징으로 하는 모스 트랜지스터의 제조방법.
  5. 제1항에 있어서, 급속열처리공정을 질소 분위기 또는 암모니아 분위기에서 수행하는 것을 특징으로 하는 모스 트랜지스터의 제조방법.
  6. 제1항에 있어서, 이온 주입시 30keV정도의 가속에너지를 갖는 상용의 이온주입 장치를 이용하는 것을 특징으로 하는 모스 트랜지스터의 제조방법.
  7. 제1항에 있어서, 남아있는 티타늄질화막(46)과 TixNyOz막(48)을 NH40H/H202용액이나 다른 산용액중 하나로 제거하는 것을 특징으로 하는 모스 트랜지스터의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930028018A 1993-12-16 1993-12-16 얕은 접합의 소오스/드레인영역과 실리사이드를 갖는 모스트랜지스터의 제조방법 KR0135163B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019930028018A KR0135163B1 (ko) 1993-12-16 1993-12-16 얕은 접합의 소오스/드레인영역과 실리사이드를 갖는 모스트랜지스터의 제조방법
US08/190,664 US5607884A (en) 1993-12-16 1994-02-02 Method for fabricating MOS transistor having source/drain region of shallow junction and silicide film
DE4406849A DE4406849C2 (de) 1993-12-16 1994-03-02 Verfahren zur Herstellung eines MOS-Transistors mit einem einen flachen Übergang aufweisenden Source/Drain-Bereich und einer Silicidschicht
JP6163338A JP2819240B2 (ja) 1993-12-16 1994-06-23 浅い接合のソース／ドレーン領域とシリサイドを有するｍｏｓトランジスタの製造方法

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KR1019930028018A KR0135163B1 (ko) 1993-12-16 1993-12-16 얕은 접합의 소오스/드레인영역과 실리사이드를 갖는 모스트랜지스터의 제조방법

Publications (2)

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KR950021525A true KR950021525A (ko) 1995-07-26
KR0135163B1 KR0135163B1 (ko) 1998-04-22

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US (1) US5607884A (ko)
JP (1) JP2819240B2 (ko)
KR (1) KR0135163B1 (ko)
DE (1) DE4406849C2 (ko)

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Publication number Publication date
JP2819240B2 (ja) 1998-10-30
KR0135163B1 (ko) 1998-04-22
DE4406849A1 (de) 1995-06-22
DE4406849C2 (de) 1996-02-01
US5607884A (en) 1997-03-04
JPH07202195A (ja) 1995-08-04

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