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KR950021050A - Wafer step relaxation method - Google Patents

Wafer step relaxation method Download PDF

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Publication number
KR950021050A
KR950021050A KR1019930030776A KR930030776A KR950021050A KR 950021050 A KR950021050 A KR 950021050A KR 1019930030776 A KR1019930030776 A KR 1019930030776A KR 930030776 A KR930030776 A KR 930030776A KR 950021050 A KR950021050 A KR 950021050A
Authority
KR
South Korea
Prior art keywords
wafer
relaxation method
wafer step
pattern
dummy pattern
Prior art date
Application number
KR1019930030776A
Other languages
Korean (ko)
Inventor
이영철
박상호
김상익
구영모
김세정
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930030776A priority Critical patent/KR950021050A/en
Publication of KR950021050A publication Critical patent/KR950021050A/en

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  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 웨이퍼의 단차가 낮은 지역(B 지역)에 전기적으로 고립된 더미패턴(5)을 형성하되 웨이퍼의 단차를 일으키는 원인이 되는 패턴(1)형성시 이 패턴(1)과 같은 층(layer) 상에 더미패턴을 형성하는 것을 특징으로 하는 웨이퍼의 단차 완화 방법에 관한 것으로, 소자를 제조하기 위한 식각공정등의 문제점을 해결하여 소자의 신뢰도 및 생산성을 향상 시키는 효과가 있다.The present invention forms a dummy pattern 5 electrically isolated in a region where the step height of the wafer is low (area B), but when forming the pattern 1 causing the wafer step, the same layer as the pattern 1 is formed. The present invention relates to a method for alleviating the step difference of a wafer, wherein a dummy pattern is formed on the wafer).

Description

웨이퍼의 단차 완화 방법Wafer step relaxation method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 소정의 반도체 소자 제조시 단차가 심하게 나타난 웨이퍼 단면도.FIG. 1 is a cross-sectional view of a wafer in which a step is severely produced in manufacturing a semiconductor device. FIG.

Claims (2)

웨이퍼의 단차 완화 방법에 있어서, 웨이퍼의 단차가 낮은 지역(B 지역)에 전기적으로 고립된 더미패턴(5)을 형성하되 웨이퍼의 단차를 일으키는 원인이 되는 패턴(1)형성시 이 패턴(1)과 같은 층(layer) 상에 더미패턴을 형성하는 것을 특징으로 하는 웨이퍼의 단차 완화 방법.In the wafer step relaxation method, a dummy pattern 5 which is electrically isolated is formed in a region (B region) where the step height of the wafer is low. Forming a dummy pattern on a layer such as (Layer) Wafer step reduction method characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930030776A 1993-12-29 1993-12-29 Wafer step relaxation method KR950021050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930030776A KR950021050A (en) 1993-12-29 1993-12-29 Wafer step relaxation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930030776A KR950021050A (en) 1993-12-29 1993-12-29 Wafer step relaxation method

Publications (1)

Publication Number Publication Date
KR950021050A true KR950021050A (en) 1995-07-26

Family

ID=66853625

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930030776A KR950021050A (en) 1993-12-29 1993-12-29 Wafer step relaxation method

Country Status (1)

Country Link
KR (1) KR950021050A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100317776B1 (en) * 1998-10-15 2002-03-20 이종수 Output diagnosis circuit of protective relay
KR100728947B1 (en) * 2001-06-29 2007-06-15 주식회사 하이닉스반도체 Exposure Method Using Reticle for Semiconductor Device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100317776B1 (en) * 1998-10-15 2002-03-20 이종수 Output diagnosis circuit of protective relay
KR100728947B1 (en) * 2001-06-29 2007-06-15 주식회사 하이닉스반도체 Exposure Method Using Reticle for Semiconductor Device

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19931229

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid