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KR950027970A - Semiconductor manufacturing method - Google Patents

Semiconductor manufacturing method Download PDF

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Publication number
KR950027970A
KR950027970A KR1019940005501A KR19940005501A KR950027970A KR 950027970 A KR950027970 A KR 950027970A KR 1019940005501 A KR1019940005501 A KR 1019940005501A KR 19940005501 A KR19940005501 A KR 19940005501A KR 950027970 A KR950027970 A KR 950027970A
Authority
KR
South Korea
Prior art keywords
pattern
semiconductor manufacturing
forming
layer
dummy pattern
Prior art date
Application number
KR1019940005501A
Other languages
Korean (ko)
Other versions
KR0121559B1 (en
Inventor
유의규
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940005501A priority Critical patent/KR0121559B1/en
Publication of KR950027970A publication Critical patent/KR950027970A/en
Application granted granted Critical
Publication of KR0121559B1 publication Critical patent/KR0121559B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 단차를 발생시키는 원인이되는 층(layer)의 패턴 형성시 그 층에 여분의 더미패턴을 이웃하는 패턴과 동일하게 형성하여 단차를 완화 시키므로써 이후의 공정마진을 확보하여 소자의 신뢰성 및 수율을 향상 시키는 효과가 있다.In the present invention, when the pattern of the layer causing the step is formed, an extra dummy pattern is formed on the layer in the same manner as the neighboring pattern to alleviate the step so that the subsequent process margin is secured so that the reliability of the device and It is effective to improve the yield.

Description

반도체 제조 방법Semiconductor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명의 일실시예에 따른 반도체 제조 공정도.2A to 2D are semiconductor manufacturing process diagrams according to one embodiment of the present invention.

Claims (1)

반도체 제조 공정중 소정 층(layer)의 패턴과 패턴 사이에 실제 소자의 동작에는 사용되지 않는 더미패턴을 형성하여 단차를 완화시키는 반도체 제조방법에 있어서; 상기 층의 패턴 형성시 이 패턴과 동일한 폭과 길이로 더미 패턴을 형성하는 것을 포함하여 이루어지는 것을 특징으로 하는 반도체 제조 방법.A semiconductor manufacturing method for reducing a step by forming a dummy pattern that is not used for the operation of an actual device between a pattern and a pattern of a predetermined layer during a semiconductor manufacturing process; And forming a dummy pattern in the same width and length as the pattern when forming the pattern of the layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940005501A 1994-03-18 1994-03-18 Manufacturing method of semiconductor device KR0121559B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940005501A KR0121559B1 (en) 1994-03-18 1994-03-18 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940005501A KR0121559B1 (en) 1994-03-18 1994-03-18 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
KR950027970A true KR950027970A (en) 1995-10-18
KR0121559B1 KR0121559B1 (en) 1997-11-11

Family

ID=19379181

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940005501A KR0121559B1 (en) 1994-03-18 1994-03-18 Manufacturing method of semiconductor device

Country Status (1)

Country Link
KR (1) KR0121559B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487506B1 (en) * 1998-01-15 2005-08-12 삼성전자주식회사 A method for planarizing an inter-layered dielectric layer with dummy pattern

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487506B1 (en) * 1998-01-15 2005-08-12 삼성전자주식회사 A method for planarizing an inter-layered dielectric layer with dummy pattern

Also Published As

Publication number Publication date
KR0121559B1 (en) 1997-11-11

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