[go: up one dir, main page]

KR940020587A - Double Gate Thin Film Transistor Structure and Manufacturing Method Thereof - Google Patents

Double Gate Thin Film Transistor Structure and Manufacturing Method Thereof Download PDF

Info

Publication number
KR940020587A
KR940020587A KR1019930002841A KR930002841A KR940020587A KR 940020587 A KR940020587 A KR 940020587A KR 1019930002841 A KR1019930002841 A KR 1019930002841A KR 930002841 A KR930002841 A KR 930002841A KR 940020587 A KR940020587 A KR 940020587A
Authority
KR
South Korea
Prior art keywords
thin film
film transistor
gate
manufacturing
double gate
Prior art date
Application number
KR1019930002841A
Other languages
Korean (ko)
Other versions
KR960002103B1 (en
Inventor
손광식
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019930002841A priority Critical patent/KR960002103B1/en
Publication of KR940020587A publication Critical patent/KR940020587A/en
Application granted granted Critical
Publication of KR960002103B1 publication Critical patent/KR960002103B1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes

Landscapes

  • Thin Film Transistor (AREA)

Abstract

본 발명은 반도체 소자의 제조공정 중 박막트랜지스터 제조시 드레인단에서의 전장의 세기와 중복 커패시턴스를 줄여 오프셋의 길이를 축소할 수 있는 여유를 갖기 위해 이중 게이트 구조의 박막 트랜지스터에서 한 개의 게이트 길이가 다른 한 개의 게이트 길이에 비해 짧은 길이를 갖는 것을 특징으로 하는 구조에 관한 것이다.According to the present invention, one gate length is different in a double-gate thin film transistor in order to reduce the length of the offset by reducing the strength of the electric field at the drain terminal and the overlap capacitance in the manufacturing of the thin film transistor during the manufacturing process of the semiconductor device. It relates to a structure characterized by having a short length compared to one gate length.

Description

이중 게이트 박막트랜지스터 구조 및 그 제조방법Double Gate Thin Film Transistor Structure and Manufacturing Method Thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 이중 게이트 구조의 박막 트랜지스터 단면도,2 is a cross-sectional view of a thin film transistor having a double gate structure according to the present invention;

제3도는 본 발명에 의한 평탄화된 이중게이트 구조의 박막 트랜지스터 단면도.3 is a cross-sectional view of a thin film transistor having a planarized double gate structure according to the present invention.

Claims (3)

박막트랜지스터 채널(4), 상기 채널(4) 상하에 각각 형성되는 상층 게이트 산화막(5)과 하층 게이트 산화막(3), 상기 상·하층게이트 산화막의 상·하에 각각 형성되는 상층 게이트(7)와 하층게이트(6)을 갖는 이중 게이트 박막트랜지스터에 있어서, 상기 이중 게이트 구조의 박막트랜지스터의 상층 게이트(7)와 하층게이트(6)가 박막트랜지스터의 드레인단에서 오버랩(over lap)되지 않도록 상기 상층 게이트(7)또는 하층게이트(6)중 어느 하나를 짧게 형성하는 것을 포함하여 이루어지는 것을 특징으로 하는 이중 게이트 박막 트랜지스터.A thin film transistor channel 4, an upper gate oxide film 5 formed above and below the channel 4, a lower gate oxide film 3, and an upper gate 7 formed above and below the upper and lower gate oxide films, respectively; In a double gate thin film transistor having a lower gate 6, the upper gate 7 and the lower gate 6 of the double gate structure thin film transistor do not overlap at the drain terminal of the thin film transistor. (7) A double gate thin film transistor comprising a short formation of any one of the lower gates (6). 이중 게이트 박막트랜지스터 제조방법에 있어서, 하층절연막(1)상에 하층게이트(6), 하층게이트산화막(3), 박막트랜지스터 채널(4), 소스(8), 드레인(9)을 형성하는 제1단계와, 상기 박막트랜지스터 채널(4)상에 상층 게이트산화막(5)을 형성하고 상기 드레인(9)단에서 상기 하층게이트(6)길이와 다르게 상층게이트(7)를 적층하는 제2단계를 포함하여 이루어지는 것을 특징으로 하는 이중게이트 구조의 박막트랜지스터 제조방법.In the method of manufacturing a double gate thin film transistor, a first layer of forming a lower gate 6, a lower gate oxide film 3, a thin film transistor channel 4, a source 8, and a drain 9 on the lower insulating film 1. And a second step of forming an upper gate oxide film 5 on the thin film transistor channel 4 and stacking the upper gate 7 at a length different from the length of the lower gate 6 at the drain 9. The method of manufacturing a thin film transistor having a double gate structure. 제2항에 있어서, 상기 제1단계는 하층게이트(6) 상부를 평탄화하는 평탄화단계를 더 포함하고 있는 것을 특징으로 하는 이중게이트 구조의 박막트랜지스터 제조방법.3. The method of claim 2, wherein the first step further comprises a planarization step of planarizing an upper portion of the lower layer gate (6). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019930002841A 1993-02-26 1993-02-26 Double Gate Thin Film Transistor Structure and Manufacturing Method Thereof KR960002103B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930002841A KR960002103B1 (en) 1993-02-26 1993-02-26 Double Gate Thin Film Transistor Structure and Manufacturing Method Thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930002841A KR960002103B1 (en) 1993-02-26 1993-02-26 Double Gate Thin Film Transistor Structure and Manufacturing Method Thereof

Publications (2)

Publication Number Publication Date
KR940020587A true KR940020587A (en) 1994-09-16
KR960002103B1 KR960002103B1 (en) 1996-02-10

Family

ID=19351360

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930002841A KR960002103B1 (en) 1993-02-26 1993-02-26 Double Gate Thin Film Transistor Structure and Manufacturing Method Thereof

Country Status (1)

Country Link
KR (1) KR960002103B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100503722B1 (en) * 2000-05-15 2005-07-26 인터내셔널 비지네스 머신즈 코포레이션 Self-aligned double gate mosfet with separate gates
US9412769B2 (en) 2013-08-05 2016-08-09 Samsung Electronics Co., Ltd. Transistor, method of manufacturing the transistor, and electronic device including the transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100503722B1 (en) * 2000-05-15 2005-07-26 인터내셔널 비지네스 머신즈 코포레이션 Self-aligned double gate mosfet with separate gates
US9412769B2 (en) 2013-08-05 2016-08-09 Samsung Electronics Co., Ltd. Transistor, method of manufacturing the transistor, and electronic device including the transistor

Also Published As

Publication number Publication date
KR960002103B1 (en) 1996-02-10

Similar Documents

Publication Publication Date Title
KR910017674A (en) Thin film transistor
KR910017676A (en) Thin film transistor
KR930017218A (en) Thin Film Field Effect Transistors and Manufacturing Method Thereof
KR950034836A (en) Insulated gate field effect transistor and its manufacturing method
KR970060510A (en) Semiconductor device and manufacturing method thereof
US6501134B1 (en) Ultra thin SOI devices with improved short-channel control
KR950021529A (en) Planar structure MOS transistor and manufacturing method thereof
KR960002880A (en) Silicon on Insulator (SOI) Transistors
KR940020587A (en) Double Gate Thin Film Transistor Structure and Manufacturing Method Thereof
US20020167049A1 (en) Field-effect transistor and manufacture thereof
KR930022601A (en) Manufacturing Method of Semiconductor Device
JPS59121979A (en) High voltage insulated gate type semiconductor device
KR920015641A (en) Method for manufacturing semiconductor device with field effect transistor
KR960026904A (en) Thin film transistor manufacturing method
KR950009808B1 (en) Thin film transistor and its manufacturing method
KR970004063A (en) MOS transistor manufacturing method
KR970053085A (en) Manufacturing Method of Thin Film Transistor
KR970024260A (en) Transistors with Oxides Under Channel Region
JPS56101758A (en) Semiconductor device
KR960006077A (en) Thin film transistor and its manufacturing method
KR930011311A (en) CMOS inverter structure and manufacturing method
KR950021500A (en) Transistor Formation Method of Semiconductor Device
JPH05136408A (en) Semiconductor device
KR970018718A (en) Manufacturing method of thin film transistor with increased offset length
JPS5666073A (en) Insulating gate type field-effect transistor

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19930226

PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 19930226

Comment text: Request for Examination of Application

PG1501 Laying open of application
G160 Decision to publish patent application
PG1605 Publication of application before grant of patent

Comment text: Decision on Publication of Application

Patent event code: PG16051S01I

Patent event date: 19960118

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19960506

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19960725

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19960725

End annual number: 3

Start annual number: 1

PR1001 Payment of annual fee

Payment date: 19990201

Start annual number: 4

End annual number: 4

PR1001 Payment of annual fee

Payment date: 20000126

Start annual number: 5

End annual number: 5

PR1001 Payment of annual fee

Payment date: 20010117

Start annual number: 6

End annual number: 6

PR1001 Payment of annual fee

Payment date: 20020116

Start annual number: 7

End annual number: 7

PR1001 Payment of annual fee

Payment date: 20030120

Start annual number: 8

End annual number: 8

PR1001 Payment of annual fee

Payment date: 20040119

Start annual number: 9

End annual number: 9

PR1001 Payment of annual fee

Payment date: 20050120

Start annual number: 10

End annual number: 10

PR1001 Payment of annual fee

Payment date: 20060118

Start annual number: 11

End annual number: 11

PR1001 Payment of annual fee

Payment date: 20061211

Start annual number: 12

End annual number: 12

PR1001 Payment of annual fee

Payment date: 20080102

Start annual number: 13

End annual number: 13

FPAY Annual fee payment

Payment date: 20090121

Year of fee payment: 14

PR1001 Payment of annual fee

Payment date: 20090121

Start annual number: 14

End annual number: 14

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee