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KR960026904A - Thin film transistor manufacturing method - Google Patents

Thin film transistor manufacturing method Download PDF

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Publication number
KR960026904A
KR960026904A KR1019940036938A KR19940036938A KR960026904A KR 960026904 A KR960026904 A KR 960026904A KR 1019940036938 A KR1019940036938 A KR 1019940036938A KR 19940036938 A KR19940036938 A KR 19940036938A KR 960026904 A KR960026904 A KR 960026904A
Authority
KR
South Korea
Prior art keywords
layer
forming
channel
polysilicon
polysilicon layer
Prior art date
Application number
KR1019940036938A
Other languages
Korean (ko)
Inventor
최국선
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940036938A priority Critical patent/KR960026904A/en
Publication of KR960026904A publication Critical patent/KR960026904A/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs

Landscapes

  • Thin Film Transistor (AREA)

Abstract

본 발명은 반도체 소자 제조공정중 트랜지스터 제조방법에 관한 것으로, 채널용 폴리실리콘층이 형성되지 않는 지역에 폴리실리콘층과의 식각선택비가 우수한 절연층을 형성함으로써 후속 공정인 채널 폴리실리콘층 식각시 과도식각으로 인한 하부층의 충격을 방지하는 것을 특징으로 한다.The present invention relates to a transistor manufacturing method in a semiconductor device manufacturing process, by forming an insulating layer having an excellent etching selectivity with the polysilicon layer in the region where the polysilicon layer for the channel is not formed is excessive during the subsequent process of channel polysilicon layer etching It is characterized by preventing the impact of the lower layer due to etching.

Description

박막 트랜지스터 제조방법Thin film transistor manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2A도 내지 제2D도는 본 발명의 일실시예에 따른 트랜지스터 제조공정 단면도.2A through 2D are cross-sectional views of a transistor manufacturing process according to an embodiment of the present invention.

Claims (6)

반도체 소자 제조공정중 트랜지스터 제조방법에 있어서, 채널용 폴리실리콘층이 형성되지 않는 지역에 폴리실리콘층과의 식각선택비가 우수한 절연층을 형성함으로써 후속 공정인 채널 폴리실리콘층 식각시 과도식각으로 인한 하부층의 충격을 방지하는 것을 특징으로 하는 박막 트랜지스터 제조방법.In the transistor manufacturing method of the semiconductor device manufacturing process, by forming an insulating layer having an excellent etching selectivity with the polysilicon layer in the region where the polysilicon layer for the channel is not formed, the lower layer due to the excessive etching during the subsequent etching of the channel polysilicon layer Method of manufacturing a thin film transistor, characterized in that to prevent the impact of. 제1항에 있어서, 상기 절연층은 게이트산화층, 게이트폴리실리콘층을 형성하는 제1단계; 폴리실리콘과의 식각 선택비(selectivity)가 우수한 절연층을 형성하는 제2단계; 채널이 형성될 영역에 존재하는 상기 절연층을 제거하는 제3단계를 포함하여 이루어지는 것을 특징으로 하는 박막 트랜지스터 제조방법.The method of claim 1, wherein the insulating layer comprises: a first step of forming a gate oxide layer and a gate polysilicon layer; Forming a dielectric layer having an excellent etching selectivity with polysilicon; And removing the insulating layer existing in the region where the channel is to be formed. 제2항에 있어서, 상기 제2단계의 절연층은 산화층과 질화층의 적층구조로 이루어지는 것을 특징으로 하는 박막 트랜지스터 제조방법.The method of claim 2, wherein the insulating layer of the second step comprises a stacked structure of an oxide layer and a nitride layer. 제3항에 있어서, 상기 산화층과 절연층을 합한 두께는 이후 형성될 게이트산화층의 두께와 유사하도록 형성되는 것을 특징으로 하는 박막 트랜지스터 제조방법.The method of claim 3, wherein the thickness of the oxide layer and the insulating layer is formed to be similar to a thickness of a gate oxide layer to be formed later. 제2항 또는 제3항에 있어서, 상기 제3단계 후 게이트산화층, 채널형성용 폴리실리콘층을 차례로 형성하는 제4단계; 소스/드레인 형성용 이온주입 공정 후 상기 채널형성용 폴리실리콘층을 선택식각하는 제5단계를 더 포함하여 이루어지는 것을 특징으로 하는 박막 트랜지스터 제조방법.The method of claim 2 or 3, further comprising: a fourth step of sequentially forming a gate oxide layer and a channel forming polysilicon layer after the third step; And a fifth step of selectively etching the channel forming polysilicon layer after the source / drain forming ion implantation process. 제5항에 있어서, 상기 제4단계 후 SPG 공정으로 결정입자의 크기를 크게하는 제6단계를 더 포함하여 이루어지는 것을 특징으로 하는 박막 트랜지스터 제조방법.6. The method of claim 5, further comprising a sixth step of increasing the size of the crystal grains in the SPG process after the fourth step. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940036938A 1994-12-26 1994-12-26 Thin film transistor manufacturing method KR960026904A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940036938A KR960026904A (en) 1994-12-26 1994-12-26 Thin film transistor manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940036938A KR960026904A (en) 1994-12-26 1994-12-26 Thin film transistor manufacturing method

Publications (1)

Publication Number Publication Date
KR960026904A true KR960026904A (en) 1996-07-22

Family

ID=66769636

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940036938A KR960026904A (en) 1994-12-26 1994-12-26 Thin film transistor manufacturing method

Country Status (1)

Country Link
KR (1) KR960026904A (en)

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