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KR930011311A - CMOS inverter structure and manufacturing method - Google Patents

CMOS inverter structure and manufacturing method Download PDF

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Publication number
KR930011311A
KR930011311A KR1019910020284A KR910020284A KR930011311A KR 930011311 A KR930011311 A KR 930011311A KR 1019910020284 A KR1019910020284 A KR 1019910020284A KR 910020284 A KR910020284 A KR 910020284A KR 930011311 A KR930011311 A KR 930011311A
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South Korea
Prior art keywords
forming
drain
conductive
mos transistor
conductive type
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KR1019910020284A
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Korean (ko)
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KR100192470B1 (en
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장태식
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문정환
금성일렉트론 주식회사
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Publication of KR930011311A publication Critical patent/KR930011311A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 종래의 CMOS에 있어서, 웰형성을 위해 넓은 면적이 피료했던 단점을 필효했던 단점을 보완하고 게이트를 공유하게 하여, 집적도를 향상시킬 수 있는 CMOS인버터 구조 및 제조방법에 관한 것으로, 제1도전형의 기판에 제1도전형과 반대되는 제2도전형의 모스트랜지스터를 형성하고, 그위에 게이트를 공유하고 제2전도형 모스트랜지스터의 소오스/드레인과 연결된 제1도전형의 소오스/드레인을 갖는 제1도전형의 모스트랜지스터가 형성된 CMOS구조로써, 그제조방법은, 제1도전형의 기판위에 게이틀ㄹ 형성하고 제1도전형과 반대되는 제2도전형의 소오스/드레인을 형성하여 제2도전형의 모스트랜지스터를 형성하는 공정과, 전표면에 격리용막을 중착하고 제2도전형 모스트랜지스터의 드레인 콘택홀을 형성하는 공정과, 상기 드레인 콘택홀에 전도체층을 선택적으로 형성하여 평탄화하고 상기 게이트 표면까지 에치백하는 공정과, 제1도전형의 모스트랜지스터의 형성을 위한 게이트 산화막을 상기 전도체층위를 제외한 부분에 형성하고 제2도전형으로 도핑된 폴리실리콘을 증착하는 공정과, 상기 증착된 폴리실리콘에 채널영역을 정의하여 제1도전형의 소오스드레인을 형성하여 제1도전형의 모스트랜지스터를 형성하는 공정으로 이루어진다.The present invention relates to a CMOS inverter structure and a manufacturing method which can improve the degree of integration by compensating for the disadvantage that a large area has been applied for well formation in the conventional CMOS and sharing a gate. A second conductive MOS transistor opposite to the first conductive type is formed on the conductive substrate, and a source / drain of the first conductive type connected to the source / drain of the second conductive MOS transistor is shared thereon. A CMOS structure in which a first transistor having a first transistor having a first conductivity type is formed. The manufacturing method includes forming a gate on a substrate of the first conductive type and forming a source / drain of a second conductive type opposite to the first conductive type. Forming a two-conductor morph transistor, depositing an isolation film on the entire surface and forming a drain contact hole of the second conductive morph transistor, and a conductor in the drain contact hole. A process of selectively forming and planarizing a layer and etching back to the gate surface, and forming a gate oxide film for forming a first transistor of a first transistor type on a portion other than the conductor layer and doped with a second conductive type And forming a channel region in the deposited polysilicon to form a source drain of the first conductivity type, thereby forming a first transistor type MOS transistor.

Description

CMOS 인버터 구조 및 제조방법CMOS inverter structure and manufacturing method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 인버터 회로 구성도,3 is an inverter circuit configuration diagram,

제4도는 본 발명의 CMOS 인버터 제조공정 단면도,4 is a cross-sectional view of the CMOS inverter manufacturing process of the present invention,

제5도는 본 발명의 CMOS 인버터 완성단면도.5 is a completed cross-sectional view of a CMOS inverter of the present invention.

Claims (3)

제1도전형 기판위에 게이트가 형성되고, 게이트 양측의 하부에 제1도전형과 반대인 제2도전형의 소오스/드레인이 형성되어 제2도전형의 모스트랜지스터가 형성되고, 상기 제2도전형 모스트랜지스터의 상축부위에, 제2도전형 모스트랜지스터의 게이틀ㄹ 공유하고 제1도전형의 소오스/드레인이 형성되어 제1도전형의 모스트랜지스터가 형성되고, 상기 제2도전형 모스트랜지스터의 소오스/드레인과 제1도전형 모스트랜지스ㅓㅌ의 소오스/드레인이 연결된 CMOS인버터 구조.A gate is formed on the first conductive type substrate, and a source / drain of the second conductive type opposite to the first conductive type is formed on both lower sides of the gate to form a second transistor type MOS transistor, and the second conductive type is formed. On the upper axis of the MOS transistor, a gate of the second conductive type MOS transistor is shared and a source / drain of the first conductive type is formed to form a MOS transistor of the first conductive type, and a source of the second conductive MOS transistor is formed. CMOS inverter structure connected to drain and source / drain of first conductivity type MOS transistor. 제1도전형의 기판에 필드영역과 액티브영역을 한정하고 액티브영역상에 게이트를 형성하는 공정과, 게이트 양측하부에 제2도전형의 소오스/드레인을 형성하여 제2도전형의 모스트랜지스터를 형성하는 공정과, 전표면에 격리용 절연막을 중착하고 상기 제2도전형 모스트랜지스터의 드레인 콘택홀을 형성하는 공정과, 드레인 콘택홀에전도체층을 형성하고 평탄화하여 상기 제2도전형 모스트랜지서트의 게이트 표면까지 에치백하여 게이트 산화막을 형성하는 공정과, 상기 전도체층위의 게이트 산화막을 제거하고 제2도전형으로 도핑된 폴리실리콘을 전도체층에 연결되게 증착하는 공정과, 증착된 폴리실리콘의 채널영역을 한정하고 제2도전형 모스트랜지스터의 소오스/드레인과 연결되게 제1도전형의 소오스/드레인을 형성하여 게이트를 공유한 제1도전형의 모스트랜지스터를 형성하고, 금속전극을 형성하는 공정으로 이루어짐을 특징으로 하는 CMOS인버터 제조방법.Forming a gate on the active region by defining a field region and an active region on the substrate of the first conductive type, and forming a second transistor type MOS transistor by forming a source / drain of the second conductive type on both lower sides of the gate. And forming a drain contact hole of the second conductive MOS transistor by depositing an insulating insulating film on the entire surface of the second conductive MOS transistor, and forming and planarizing a conductor layer in the drain contact hole. Etching back to the gate surface to form a gate oxide film, removing the gate oxide film on the conductor layer, depositing polysilicon doped with a second conductivity type to be connected to the conductor layer, and channel region of the deposited polysilicon FIG. 1 is a first conductive type source / drain connected to the source / drain of the second conductive type MOS transistor and the gate is shared. A method of manufacturing a CMOS inverter, comprising forming a typical MOS transistor and forming a metal electrode. 제1항 또는 제2항에 있어서, 전도체층은 실리사이드를 이용함을 특징으로 하는 CMOS인버터 구조 및 제조방법.3. The structure and fabrication method of a CMOS inverter according to claim 1 or 2, wherein the conductor layer uses silicide. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910020284A 1991-11-14 1991-11-14 CMS inverter structure and manufacturing method KR100192470B1 (en)

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KR1019910020284A KR100192470B1 (en) 1991-11-14 1991-11-14 CMS inverter structure and manufacturing method

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Application Number Priority Date Filing Date Title
KR1019910020284A KR100192470B1 (en) 1991-11-14 1991-11-14 CMS inverter structure and manufacturing method

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KR930011311A true KR930011311A (en) 1993-06-24
KR100192470B1 KR100192470B1 (en) 1999-07-01

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KR102446823B1 (en) 2017-06-16 2022-09-26 삼성디스플레이 주식회사 Display device and manufacturing method thereof

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