KR930002816B1 - 리드프레임의 가공방법 - Google Patents
리드프레임의 가공방법 Download PDFInfo
- Publication number
- KR930002816B1 KR930002816B1 KR1019890017849A KR890017849A KR930002816B1 KR 930002816 B1 KR930002816 B1 KR 930002816B1 KR 1019890017849 A KR1019890017849 A KR 1019890017849A KR 890017849 A KR890017849 A KR 890017849A KR 930002816 B1 KR930002816 B1 KR 930002816B1
- Authority
- KR
- South Korea
- Prior art keywords
- plating
- lead
- circuit pattern
- lead frame
- dam bar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (1)
- 외부리드사이를 연결하는 댐바를 갖고 적어도 내부리드의 도금필요장소에 은도금, 금도금등의 부분도금이 행해지는 리드프레임의 가공방법에 있어서, 형성해야할 회로패턴중 반도체장치에 조립했을때 반도체장치 본체내에서 또 상기 도금필요장소에 도달되지 않는 위치와 상기 댐바와의 사이의 회로패턴을 제외하고 적어도 상기 도금필요장소가 되는 부분의 회로패턴의 적어도 측단면을 형성하는 가공을 행하고 그런후에 상기 도금 필요장소에 소요부분 도금을 행하고 다음에 남은 미가공부분의 회로패턴을 형성시키는 가공을 행하는 것을 특징으로 하는 리드프레임의 가공방법.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63308361A JP2648353B2 (ja) | 1988-12-06 | 1988-12-06 | リードフレームの製造方法 |
JP63-308361 | 1988-12-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900010984A KR900010984A (ko) | 1990-07-11 |
KR930002816B1 true KR930002816B1 (ko) | 1993-04-10 |
Family
ID=17980140
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890017849A Expired - Fee Related KR930002816B1 (ko) | 1988-12-06 | 1989-12-04 | 리드프레임의 가공방법 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2648353B2 (ko) |
KR (1) | KR930002816B1 (ko) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100641512B1 (ko) | 2002-12-30 | 2006-10-31 | 동부일렉트로닉스 주식회사 | 반도체 패키지 공정에서의 리드 프레임 구조 |
KR100789419B1 (ko) * | 2006-11-27 | 2007-12-28 | (주)원일사 | 리드프레임 모재 가공방법 |
JP6518547B2 (ja) * | 2015-08-07 | 2019-05-22 | 新光電気工業株式会社 | リードフレーム、半導体装置及びリードフレームの製造方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55151357A (en) * | 1979-05-16 | 1980-11-25 | Nec Corp | Lead frame for semiconductor device |
-
1988
- 1988-12-06 JP JP63308361A patent/JP2648353B2/ja not_active Expired - Fee Related
-
1989
- 1989-12-04 KR KR1019890017849A patent/KR930002816B1/ko not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR900010984A (ko) | 1990-07-11 |
JP2648353B2 (ja) | 1997-08-27 |
JPH02154454A (ja) | 1990-06-13 |
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