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KR920022295A - 높은 출력 이득을 얻는 데이타 출력 드라이버 - Google Patents

높은 출력 이득을 얻는 데이타 출력 드라이버 Download PDF

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Publication number
KR920022295A
KR920022295A KR1019910008756A KR910008756A KR920022295A KR 920022295 A KR920022295 A KR 920022295A KR 1019910008756 A KR1019910008756 A KR 1019910008756A KR 910008756 A KR910008756 A KR 910008756A KR 920022295 A KR920022295 A KR 920022295A
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KR
South Korea
Prior art keywords
input line
data output
transistor
signal
output driver
Prior art date
Application number
KR1019910008756A
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English (en)
Other versions
KR940006998B1 (ko
Inventor
이승근
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910008756A priority Critical patent/KR940006998B1/ko
Priority to US07/724,889 priority patent/US5157279A/en
Priority to JP3244105A priority patent/JPH0746511B2/ja
Publication of KR920022295A publication Critical patent/KR920022295A/ko
Application granted granted Critical
Publication of KR940006998B1 publication Critical patent/KR940006998B1/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음.

Description

높은 출력 이득을 얻는 데이타 출력 드라이버
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 따른 데이타 출력 드라이버의 실시예,
제4도는 본 발명에 따른 데이타 출력 드라이버의 타이밍도,
제5도는 본 발명에 따른 데이타 출력 드라이버의 수직 단면도.

Claims (6)

  1. 서로 상보적인 논리레벨을 가지는 한쌍의 신호를 각각의 게이트로 받는 제1 및 제2출력 트랜지스터를 가지는 데이타 출력 드라이버에 있어서, 상기 신호가 제1상태에 있는 경우에는 상기 제1출력 트랜지스터의 벌크에 제1신호를 공급하고 상기 신호가 제2상태에 있는 경우에는 상기 제1출력 트랜지스터의 벌크에 제2신호를 공급하는 정전압 수단을 구비함을 특징으로 하는 데이타 출력 드라이버.
  2. 제1항에 있어서, 상기 제1신호가 상기 제1상태에 있으며, 상기 제2신호가 상기 제2상태에 있음을 특징으로 하는 데이타 출력 드라이버.
  3. 제1항에 있어서, 상기 정전압 수단이 상기 제1출력 트랜지스터의 게이트에 연결된 입력라인과, 상기 입력라인에 게이트가 접속되고 전원전압단과 상기 제1출력 트랜지스터의 벌크 사이에 채널이 연결된 풀업 트랜지스터와, 상기 입력라인에 게이트가 연결되고 상기 벌크의 접지전압단 사이에 채널이 연결된 풀다운 트랜지스터를 구비함을 특징으로 하는 데이타 출력 드라이버.
  4. 제3항에 있어서, 상기 입력라인과 접지전압단 사이에 연결되고 상기 입력라인의 전위가 소정 레벨 이하인 경우에 소정의 바이어스를 상기 입력라인에 공급하는 수단이 더 구비됨을 특징으로 하는 데이타 출력 드라이버.
  5. 서로 상보적인 논리레벨을 가지는 한쌍의 신호를 각각의 게이트로 받는 제1 및 제2출력 트랜지스터를 가지는 데이타 출력 드라이버에 있어서, 상기 제1출력 트랜지스터의 게이트에 연결된 입력라인과, 상기 입력라인에 게이트가 접속되고 전원전압단과 상기 제1출력 트랜지스터의 벌크 사이에 채널이 연결된 풀업 트랜지스터와, 상기 입력라인에 게이트가 연결되고 상기 벌크와 접지전압단 사이에 채널이 연결된 풀다운 트랜지스터와, 상기 입력라인과 접지전압단 사이에 연결되고 상기 입력라인의 전위가 소정 레벨 이하인 경우에 소정의 바이어스를 상기 입력 라인에 공급하는 수단을 구비함을 특징으로 하는 데이타 출력 드라이버.
  6. 제5항에 있어서, 상기 수단이, 상기 입력라인의 전위가 TTL레벨 2.4V이하인 경우에 상기 입력라인의 전위를 접지전압단으로 방전시킴을 특징으로 하는 데이타 출력 드라이버.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910008756A 1991-05-28 1991-05-28 높은 출력 이득을 얻는 데이타 출력 드라이버 KR940006998B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019910008756A KR940006998B1 (ko) 1991-05-28 1991-05-28 높은 출력 이득을 얻는 데이타 출력 드라이버
US07/724,889 US5157279A (en) 1991-05-28 1991-07-02 Data output driver with substrate biasing producing high output gain
JP3244105A JPH0746511B2 (ja) 1991-05-28 1991-08-30 高い出力利得を得るデータ出力ドライバー

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910008756A KR940006998B1 (ko) 1991-05-28 1991-05-28 높은 출력 이득을 얻는 데이타 출력 드라이버

Publications (2)

Publication Number Publication Date
KR920022295A true KR920022295A (ko) 1992-12-19
KR940006998B1 KR940006998B1 (ko) 1994-08-03

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Country Status (3)

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US (1) US5157279A (ko)
JP (1) JPH0746511B2 (ko)
KR (1) KR940006998B1 (ko)

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JP4659826B2 (ja) 2004-06-23 2011-03-30 ペレグリン セミコンダクター コーポレーション Ｒｆフロントエンド集積回路
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US9653601B2 (en) 2005-07-11 2017-05-16 Peregrine Semiconductor Corporation Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink-harmonic wrinkle reduction
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Publication number Publication date
US5157279A (en) 1992-10-20
JPH0746511B2 (ja) 1995-05-17
KR940006998B1 (ko) 1994-08-03
JPH04355298A (ja) 1992-12-09

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