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KR920002424B1 - Frequency detection circuit - Google Patents

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KR920002424B1
KR920002424B1 KR1019880017792A KR880017792A KR920002424B1 KR 920002424 B1 KR920002424 B1 KR 920002424B1 KR 1019880017792 A KR1019880017792 A KR 1019880017792A KR 880017792 A KR880017792 A KR 880017792A KR 920002424 B1 KR920002424 B1 KR 920002424B1
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frequency
circuit
input
detection circuit
output
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KR1019880017792A
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Korean (ko)
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KR900011147A (en
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이병조
이건수
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대한전선 주식회사
유인영
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass

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  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

내용 없음.No content.

Description

주파수 검출회로Frequency detection circuit

제1도는 본 발명의 주파수 검출 회로도.1 is a frequency detection circuit diagram of the present invention.

제2도는 제1도의 각 단자점 출력 파형도.2 is a waveform diagram of each terminal point output of FIG.

제3도는 본 발명의 검출주파수 보다 높은 주파수 인가시의 출력 파형도.3 is an output waveform diagram when applying a frequency higher than the detection frequency of the present invention.

제4도는 본 고안의 검출주파수 보다 낮은 주파수 인가시의 출력 파형도.4 is an output waveform diagram when applying a frequency lower than the detection frequency of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 입력검출회로 2 : 미분회로1: input detection circuit 2: differential circuit

3 : 비교회로 4 : 카운팅회로3: comparison circuit 4: counting circuit

10 : 충방전회로 OP1-OP4: 비교기10: charge and discharge circuit OP 1 -OP 4 : comparator

FF : 플립플롭 CO : 카운터FF: Flip-flop CO: Counter

IN1-IN3: 인버터 R1-R9: 저항IN 1 -IN 3 : Inverter R 1 -R 9 : Resistance

C1-C3: 콘덴서C 1 -C 3 : Capacitor

본 발명은 주파수 검출회로에 관한 것으로서, 특히 검출주파수에 비해 비교적 높고 낮은 노이즈 주파수가 중첩 입력되면 카운트는 클리어 되도록 하여 검출하고자 하는 일정 주파수만을 정확하게 검출할 수 있도록 한 것에 주안점을 둔 것이다.The present invention relates to a frequency detection circuit, and in particular, a focus is placed on the frequency detection circuit so that when a relatively high and low noise frequency is superimposed, the count is cleared so that only a predetermined frequency can be accurately detected.

종래에는 주파수를 검출하기 위해서 RC 액티브 밴드 패스필터(Band Pass Filter)를 이용한 회로를 사용하였지만, 이는 입력주파수 레벨에 대한 출력주파수 레벨의 비이므로 상당히 레벨이 큰 노이즈에 대해서는 요구된 주파수 성분만을 검출하는 데에 부적당한 문제점을 가지고 있었다.Conventionally, a circuit using an RC active band pass filter is used to detect a frequency, but since it is a ratio of an output frequency level to an input frequency level, only a required frequency component is detected for a noise having a large level. Had an inadequate problem.

본 발명은 상기와 같은 종래의 문제점을 해결하고자, 주파수가 입력되면 히스테리시스(Hysteresis)폭을 갖는 비교회로와, 미분회로, 윈도우 비교회로(Window Comparator)와, 카운팅 회로를 통하여 설정한 시간동안 해당하는 주파수만을 검출할 수 있도록 한 것에 목적을 둔 것이다.The present invention is to solve the conventional problems as described above, when the frequency is input, the comparison circuit having a hysteresis (hysteresis) width, the differential circuit, the window comparator (Window Comparator), and the corresponding time for the set by the counting circuit The goal is to be able to detect frequencies only.

이하 첨부도면에 따라서 설명하면 다음과 같다.When described according to the accompanying drawings as follows.

제1도와 같이, 입력신호(Si)가 인가되면 콘덴서(C1)를 거쳐 저항(R1-R3)으로 기준전압을 설정한 비교기(OP1)의 반전단자(-)에 입력되도록 한 입력검출회로(1)와 ; 이 입력검출회로(1)의 출력에서 인버터(IN1)와 다이오드(D1) 그리고 콘덴서(C2) 및 저항(R4)으로 구성된 미분회로(2)를 거쳐 비교기(OP2)의 반전단자(-)에 입력시킨다.As shown in FIG. 1, when an input signal Si is applied, the input signal Si is input to the inverting terminal (-) of the comparator OP 1 having the reference voltage set by the resistors R 1- R 3 through the capacitor C 1 . Detection circuit 1; The inverting terminal of the comparator OP 2 via the differential circuit 2 composed of an inverter IN 1 , a diode D 1 , a capacitor C 2 , and a resistor R 4 at the output of the input detection circuit 1 . Enter in (-).

이 비교기(OP3)의 출력에 콘덴서(C3)와 저항(R5)으로 구성된 충방전회로(10)와, 저항(R6, R7, R8)으로 기준전압(Va, Vb)을 설정한 비교기(OP3)(OP4)에 입력시켜서 검출하고자 하는 임의 주파수를 설정하여 비교하도록 한 비교회로(3)를 구성한다.At the output of the comparator OP 3 , the charge / discharge circuit 10 composed of the capacitor C 3 and the resistor R 5 and the resistors R 6 , R 7 and R 8 are used to supply the reference voltages Va and Vb. A comparator circuit 3 configured to be inputted to the set comparator OP 3 (OP 4 ) to compare and set an arbitrary frequency to be detected.

상기 비교회로(3)의 출력(B)과 검출회로(1)의 출력(A)을 인버터(IN2)(IN3)를 거처 플립플롭(FF)과 카운터(CO)에 입력시켜서 해당하는 주파수가 입력될때 카운팅을 수행하도록 한 카운팅회로(4)를 구성하여서 된 것이다.The output B of the comparison circuit 3 and the output A of the detection circuit 1 are inputted to the flip-flop FF and the counter CO via an inverter IN 2 (IN 3 ) and corresponding frequency. Is to configure the counting circuit 4 to perform the counting when is input.

그리고 a, b, c, d, e는 각 단자점을 나타낸 것이고, 이 단자점(a, b, c, d, e)의 동작 출력파형도는 제2도, 제3도, 제4도에서 나타낸 바와 같다.And a, b, c, d, and e represent terminal points, and the operating output waveforms of the terminal points a, b, c, d, and e are shown in FIGS. As shown.

이와같은 회로로서 구성된 본 발명의 동작 및 작용효과를 설명하면 다음과 같다.Referring to the operation and effect of the present invention configured as such a circuit as follows.

입력검출회로(1)는 히스테리 시스폭을 갖는 비교회로로서 주파수가 콘덴서(C1)를 통하여 입력되면 제로레퍼런스(Zero Reference)와 비교하여 입력주파수와 같은 주기의 구형파를 발생하게 되고, 이 비교기(OP1)에 히스테리 시스폭 (Hys teresis Width)을 설정하여 입력주파수 상에서 발생하는 채터링 노이즈 (Chattering Noise)를 보상하도록 한다.The input detection circuit 1 is a comparison circuit having a hysteresis width, and when a frequency is input through the capacitor C 1 , a square wave having a period equal to the input frequency is generated in comparison with a zero reference. Set the hysteresis width to OP 1 ) to compensate for chattering noise generated on the input frequency.

상기 입력검출회로(1)의 출력신호가 발생되면, 미분회로(2)에서는 콘덴서(C2)와 저항(R4)에 의해서 미분파형으로 변형되고 다이오드(D1)를 거쳐 정(+)측 미분파형만을 출력시키는데 이 출력파형은 제2도의 (a)에 나타난 바와 같다.When the output signal of the input detection circuit 1 is generated, the differential circuit 2 is transformed into a differential waveform by the capacitor C 2 and the resistor R 4 and is positive (+) side through the diode D 1 . Only the differential waveform is output. This output waveform is shown in (a) of FIG.

상기 출력파형은 비교회로(3)에 입력되는데, 비교기(OP2)의 반전단자(-)에 입력되면, 비반전단자(+)에 설정된 기준전압(Va)과 비교하여 하이 로우신호를 출력시키고, 이 출력에 대해 비교기(OP2)의 출력측에 접속된 저항(R5)과 콘덴서(C2)에서 충방전을 일으키게 되어 제2도의 (b)와 같은 파형이 출력된다.The output waveform is input to the comparator circuit 3. When the output waveform is input to the inverting terminal (−) of the comparator OP 2 , a high low signal is output by comparing the reference voltage Va set to the non-inverting terminal (+). With respect to this output, charge and discharge are caused by the resistor R 5 and the capacitor C 2 connected to the output side of the comparator OP 2 to output a waveform as shown in FIG.

상기 콘덴서(C3)와 저항(R5)에 의해 검출하고자 하는 입력주파수의 범위가 정해지고, 입력주파수의 증가와 감소에 따라 저항(R5)과 콘덴서(C3)의 충방전회로(10)에 의해서 비교회로(3)의 비교기(OP2)의 출력파형 전압은 변화하게 된다.The capacitor (C 3) and the charge-discharge circuit (10 of resistance resistor (R 5) and a capacitor (C 3) is determined in a range of input frequencies, with the increase and decrease in the input frequency to be detected by (R 5) ), The output waveform voltage of the comparator OP 2 of the comparison circuit 3 changes.

즉 비교기(OP3)(OP4)에서 설정한 기준전압(Va)(Vb)사이에 있을때만 비교기(OP3)(OP4)의 출력전압이 하이로 출력된다.I.e., the comparator (OP 3) only when the output voltage of the comparator (OP 3) (OP 4) between (OP 4) a reference voltage (Va) (Vb) is set in the output high.

그러므로서 검출하고자 하는 주파수 값은 설정시에는 충전회로(10)의 사정수를 조정하든지 기준전압(Va, Vb)을 조정하여서 비교기(OP2)의 출력전압임 기준전압(Va, Vb)사이에 있도록 하여야 한다.Therefore, the frequency value to be detected is the output voltage of the comparator OP 2 by adjusting the number of charging circuits 10 or by adjusting the reference voltages Va and Vb at the time of setting, between the reference voltages Va and Vb. Should be available.

충방전회로(10)의 전압파형에 대한 비교기(OP2)의 출력전압(V2)은,The output voltage V 2 of the comparator OP 2 with respect to the voltage waveform of the charge / discharge circuit 10 is

Figure kpo00001
이다.
Figure kpo00001
to be.

상기에서 제2도는 검출하고자 하는 주파수가 입력되었을 경우의 파형도로서 카운터가 정상적으로 동작하며, 제3도는 검출하고자 하는 주파수 보다 높은 주파수일때의 파형도이고, 제4도는 검출하고자 하는 주파수보다 낮은 주파수일때의 파형도로서 카운터는 정상동작을 하지 않게 된다.2 is a waveform diagram when a frequency to be detected is input, and the counter operates normally. FIG. 3 is a waveform diagram when the frequency is higher than the frequency to be detected, and FIG. 4 is a frequency diagram lower than the frequency to be detected. The counter does not operate normally as a waveform diagram of.

상기 제2도, 제3도 그리고 제4도의 카운터 주기 간격을 t0, t1, t2의 관계는 아래와 같은 관계를 갖는다.The relationship between t 0 , t 1 , and t 2 in the counter cycle intervals of FIGS. 2, 3, and 4 has the following relationship.

t0＜t1＜t2 t 0 <t 1 <t 2

그리고 카운터회로(4)는 입력검출회로(1)의 출력파형(A)과 비교회로(3)의 출력파형을 입력주파수로 카운트하여 주파수 검출신호(out)를 출력시키는데, 즉 입력검출회로(1)의 출력(A)은 인버터(IN3)를 거쳐 인버팅된 펄스(e)를 플립플롭(FF)의 클럭신호(CK)로 입력되고, 비교회로(3)의 출력파형(B)은 인버터(IN2)를 거쳐 플립플롭 (FF)의 입력단(D)과 카운터(CO)의 클릭신호(CK)로 인가시킨다.The counter circuit 4 counts the output waveform A of the input detection circuit 1 and the output waveform of the comparison circuit 3 as an input frequency and outputs a frequency detection signal out, that is, the input detection circuit 1 Output A is inputted as the clock signal CK of the flip-flop FF by the inverted pulse e through the inverter IN 3 , and the output waveform B of the comparison circuit 3 is an inverter. It is applied to the input terminal D of the flip-flop FF and the click signal CK of the counter CO via (IN 2 ).

플립플롭(FF)의 출력(Q)은 카운터(CO)의 인에이블 클리어신호(CLR)로서 입력주파수에 의한 클럭신호가 인가되어도 비교회로(3)에 의해 플립플롭(FF)의 입력(D)이 로우일때만 카운팅이 인에이블 된다.The output Q of the flip-flop FF is the enable clear signal CLR of the counter CO, and the input D of the flip-flop FF is provided by the comparison circuit 3 even when a clock signal at an input frequency is applied. Only when this counting is enabled.

즉 검출하고자 하는 주파수에서만 제2도의 (e)와 같은 클럭(CLK)신호가 라이징엣지시 제3도의 (d)와 같이 플립플롭(FF)의 입력(D)이 로우가 되어 카운팅이 인에이블 되지만 제3도의 (b)와 같이 검출하고자 하는 주파수보다 높게 입력될시는 비교기(OP2)의 출력전압이 기준전압(Va)보다 낮아 입력(D)은 하이가 되어 카운터 (CO)를 클리어시킨다.That is, when the clock CLK signal as shown in (e) of FIG. 2 is rising only at the frequency to be detected, the input D of the flip-flop FF becomes low as shown in (d) of FIG. 3 at the rising edge, and counting is enabled. When the input voltage is higher than the frequency to be detected as shown in (b) of FIG. 3, the output voltage of the comparator OP 2 is lower than the reference voltage Va and the input D becomes high to clear the counter CO.

또한 제4도에서와 같이 검출하고자 하는 주파수보다 낮은 주파수가 인가될 시에는 비교기(OP2)의 출력전압이 기준전압(Vb)보다 높아 입력(D)은 플립플롭(FF)의 클럭신호(CK)의 라이징엣지시 하이가 되어 카운터(CO)를 클리어시킨다.In addition, when a frequency lower than the frequency to be detected is applied as shown in FIG. 4, the output voltage of the comparator OP 2 is higher than the reference voltage Vb, so that the input D is the clock signal CK of the flip-flop FF. The counter (CO) is cleared at the rising edge of).

따라서 카운팅은 검출하고자 하는 그 주파수보다 높거나 낮을때에는 카운터 (CO)의 클리어단자(CLR)에 하이가 인가됨에 따라 카운팅은 디스에이블되고 해당하는 주파수가 입력될때만 클리어단자(CLR)에 로우신호가 걸리게 되므로서 카운터(CO)가 인에이블되어 주파수 검출신호(out)를 생성하게 된다.Therefore, when counting is higher or lower than the frequency to be detected, high is applied to the clear terminal (CLR) of the counter (CO). Counting is disabled and a low signal is cleared to the clear terminal (CLR) only when the corresponding frequency is input. As a result, the counter CO is enabled to generate the frequency detection signal out.

이와같이 본 발명은 해당하는 주파수대 만을 검출하여 카운팅할 수 있게 되므로서, 검출하고자 하는 주파수가 어느 일정시간 동안 입력되는 도중 노이즈성의 높고, 낮은 주파수가 인가될시에는 카운터를 클리어시켜 검출하고자 하는 주파수만을 정확하게 검출할 수 있게 된 것이다.As described above, the present invention can detect and count only a corresponding frequency band, and when a high and low frequency of noise is applied while a frequency to be detected is input for a certain time, only a frequency to be detected by clearing a counter is accurately corrected. It can be detected.

Claims (3)

전화선의 팁 또는 링 입력신호(Si)를 검출하여 히스테리 시스폭을 갖는 구형파를 생성하는 입력검출회로(1)와, 상기 입력검출회로(1)의 출력구형파 펄스를 미분시켜 정극성(+)의 미분펄스만을 출력시키는 미분회로(2)와, 이로부터 출력되는 정극성 미분펄스와 기준전압(Va)을 1차 비교한 출력값에 따라 충방전펄스(V2)와 2차 비교하여 두 기준전압(Va)(Vb)의 영역내에 포함되는 해당주파수만을 출력시키는 비교회로(3)와, 상기 입력검출회로(1) 및 비교회로(3)의 출력을 인가받아 해당주파수의 입력여부에 따라 트리거신호를 인에이블 또는 클리어시키는 카운터회로(4)를 구비하여 구성됨을 특징으로 하는 주파수 검출회로.An input detection circuit 1 for generating a square wave having a hysteresis width by detecting a tip or ring input signal Si of a telephone line, and output square wave pulses of the input detection circuit 1 are differentiated to provide positive polarity (+). The differential circuit 2 which outputs only the differential pulses and the positive and negative differential pulses outputted therefrom and the reference voltage Va are first compared with the charge / discharge pulses V 2 according to the output value obtained by comparing the two reference voltages ( The comparison circuit 3 outputs only the corresponding frequency included in the area of Va) (Vb), and the output of the input detection circuit 1 and the comparison circuit 3 is applied to generate a trigger signal according to whether the corresponding frequency is input. And a counter circuit (4) for enabling or clearing. 제1항에 있어서 ; 충방전 펄스 콘덴서(C3)와 저항(R5)으로 구성되는 충방전 회로(10)에 의해 검출하고자 하는 해당주파수를 설정하도록 구성한 것을 특징으로 하는 주파수 검출회로.The method of claim 1; A frequency detection circuit, characterized in that configured to set a corresponding frequency to be detected by a charge / discharge circuit (10) composed of a charge / discharge pulse capacitor (C 3 ) and a resistor (R 5 ). 제1항에 있어서 ; 비교회로(3)의 분압저항(R6, R7, R8)으로서 상, 하폭의 기준전압(Va, Vb)를 설정하여 해당주파수를 설정하도록 구성한 것을 특징으로 하는 주파수 검출회로.The method of claim 1; A frequency detection circuit comprising a voltage divider (R 6 , R 7 , R 8 ) of the comparison circuit (3) configured to set a corresponding frequency by setting reference voltages Va and Vb of the upper and lower widths.
KR1019880017792A 1988-12-29 1988-12-29 Frequency detection circuit KR920002424B1 (en)

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KR1019880017792A KR920002424B1 (en) 1988-12-29 1988-12-29 Frequency detection circuit

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KR1019880017792A KR920002424B1 (en) 1988-12-29 1988-12-29 Frequency detection circuit

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KR900011147A KR900011147A (en) 1990-07-11
KR920002424B1 true KR920002424B1 (en) 1992-03-23

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