JPH0193206A - Pulse count type detector - Google Patents

Abstract

PURPOSE:To increase a dynamic range after detection by providing a level shift circuit at the rear stage of a digital type monostable multivibrator. CONSTITUTION:By inputting a signal to the monostable multivibrator MM7, a signal with pulse width (tau) (constant) is outputted. The pulse width (tau) can be obtained by performing the frequency division of a highly stabilized clock incorporated in the inside of the MM7. The output of the MM7 is level- converted at the level shift circuit 8. Thus, by using the digital type MM7, the pulse width is generated quite accurately except jitter and high stability can be obtained. Also, by providing the level shift circuit 8, it is possible to set an average voltage at the time of no modulation equal to the bias voltage VB of an LPF at the next stage, thereby, it is possible to improve the dynamic range of a detecting signal and to generate resistance for the offset of a carrier.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pulse count type detection device used for demodulating frequency modulated signals.

BACKGROUND OF THE INVENTION FIG. 4 shows the configuration of a conventional pulse count type detection device. In the figure, 1 is an input terminal for a frequency modulated signal, 2 is a limiter, 3 is a monostaple multivibrator (hereinafter referred to as MM), 4 is a low-pass filter, and 5 is an output terminal.

In the above configuration, the frequency modulated wave input to input terminal 1 is
The limiter 2 converts it into a binary signal (Fig. 5(a)).
), MM3 is triggered by the edge of this signal, and a signal with a constant pulse width (τb) is output (Figure 5 (b))
. At this time, when the modulation frequency becomes high, the energy of the pulse outputted by the MM3 increases, and when the modulation frequency becomes low, the energy decreases, so that an output proportional to the modulation frequency can be obtained more than the MM3. Next, the carrier component is removed from the output of the MM3 by the LPF 4, and an output voltage proportional to the input frequency is obtained as shown in FIGS. 5(c) and 6. In FIG. 5(c), Vb is the output with respect to the signal input when no modulation is performed, and corresponds to the carrier frequency.

There are two types of MM3: analog type and digital type. Of these, digital type MM inputs a stable high-speed timing lock with an external clock frequency to create timing with a constant pulse width, and divides this clock to generate timing with a constant pulse width. This method obtains timing, eliminates the need for adjustment, and is suitable for integration.

Problems to be Solved by the Invention However, in the above-mentioned conventional detection device using a digital MM, unless a reasonably high-speed clock is used, the timing error of the clock causes a delay after detection compared to an analog detection device. There was a problem that the S/N ratio was poor.

The present invention is intended to eliminate the drawbacks of the above-mentioned conventional example, and it is an object of the present invention to provide an excellent pulse count type detection device that can improve the S/N ratio with a limited clock frequency.

Means for Solving the Problems In order to achieve the above object, the present invention provides a digital M
In addition to providing a level shift circuit in M, the data ratio is changed, and the offset voltage after detection resulting from this is corrected by the level shift circuit.

Therefore, according to the present invention, it is possible to correct the voltage offset due to the fluctuation of the duty ratio that occurs when the MM pulse width is increased to prevent S/N deterioration due to jitter, so that the voltage offset after detection can be corrected by the level shift circuit. This has the effect of widening the dynamic range.

Embodiment FIGS. 1 and 2 show the structure of an embodiment of the present invention. In FIG. 1, 6 is an input terminal for a frequency modulated signal, and 7 is a digital MM whose output is connected to an input terminal 9 of a level shift circuit 8. 10 is the output terminal of the level shift circuit, and is connected to the LPF 4 in FIG. 4. FIG. 2 is a diagram explaining the level shift circuit 8 in detail.

In FIG. 2, reference numeral 9 denotes an input terminal for the output signal of the digital MM 7, which is connected to the control terminals of the inverter 12 and the switch 13. 14 is a switch whose control terminal is connected to the inverter 12. Switches 13 and 14 are switches that are turned ON when the control signal is rHJ, for example.
Since the control signal for the switch 14 is inverted by the inverter 12, the switches 13 and 14 are turned ON and OFF at opposite timings. Reference numeral 11 denotes a bias signal input terminal, which is the same as the bias signal Va of the next stage LPF 4.几.

~R4 is a voltage dividing resistor that determines the voltage of the level shift circuit 8, and divides the voltage between ① and V, ,V, and VB.

Vl (!: Vt is usually the same as the circuit power supply (■.C). For example, V, = Vcc, V, = GN
Let it be D. If the polarity of the detection signal is reversed, Vr = ON D, Vj = V=
−. Reference numeral 15 denotes a buffer for suppressing voltage fluctuations after level shift due to input impedance of the load circuit.

Next, the operation of the above embodiment will be explained. Figure 3 (dl
When the signal shown in FIG. 1 is input to the MM7 in FIG. 1, a signal with a pulse width τ (constant) is output as shown in FIG. 3(e). This pulse width τ is obtained by dividing a highly stable clock built into the MM7.

The output of MM7 is level-converted by level shift circuit 8 as shown in FIG. 3(f). Here, T is the period of the carrier when no modulation is performed, and Vn and VL are respectively set so that the average value of the signal in Fig. 3 (r) becomes VB when no modulation is performed, that is, the output of LPF4 becomes VB. Decide as follows.

Normally, τ is selected to be 1/2 (=50%), and the larger it is, the more it is possible to prevent deterioration of S due to jitter, but it is limited by the maximum frequency deviation of the signal to be detected. The maximum width of T is 7 times 1, where Δr [Hz] is the positioning deviation of the signal to be detected.
...River (1) Must be village Δf. τ is selected to be maximum within this range. Voltages Vu and VL are selected as follows.

That is, the average value voltage Vm v of the signal in FIG. 3(f)
r is Vast = (VH-Vj)-y' + Vt
, -・" (2), so that this average value voltage is equal to the bias voltage of LPF4, Vmvt = Va = (Vu - Vt,) + Vt,
``'''' (3) If VL is determined appropriately, VH = (VB-VL) - 10VL ・
- Group - (4) V) I is determined. In order to obtain VH and VL, voltage dividing resistors R1 to R1 are determined in FIG.

Resistor R+, Rt is V, and the voltage V input by the bias signal determines the division value, and resistor R3
, 4 is V, and the voltage VB input from the input terminal 11 determines the division value. For example, V+>VH>
When VB > VL > Vs, the resistances R1 and R1 are determined as follows, and the resistors R1 and R4 are determined as follows. To invert the polarity of the signal to be detected, set V,>V.

According to the above embodiment, the following effects can be obtained.

(1) A digital MM7 is used, and the pulse width is very accurate, except for jitter, and the stability is high.

Therefore, if the frequency of the clock oscillation circuit that determines the pulse width is stable with respect to the voltage, the voltage after detection is proportional only to the power supply voltage. ) If the reference voltage of the comparator for data decoding is obtained from the power supply voltage, fluctuations in the power supply voltage become completely irrelevant.

(2) Deterioration in S/N due to jitter in the digital MM7 can be minimized because the pulse width is made as large as possible.

(3) By providing the level shift circuit 8, the average voltage during non-modulation can be made the same as the bias voltage Va of the next stage LPF 4, so DC coupling is possible and the reception start-up characteristics are improved.

(4) Since the level shift circuit 8 generates between the bias voltage and the power supply voltage,
Offset after detection can be reduced.

(5) Since Vs can be selected so that the dynamic range of the LPF 4 is maximized, the dynamic range of the detected signal can be improved, and it becomes resistant to carrier offset.

(6) Since only the relative error is a problem with the dividing resistor for level shifting, it is easy to integrate the detection circuit with the digital MM7.

Effects of the Invention As explained above with reference to the embodiments, according to the present invention, since a level shift circuit is provided at the subsequent stage of the digital MM,
Since the offset voltage after detection due to the change in duty ratio that occurs when the pulse width is increased can be corrected by level shifting, it is possible to reduce jitter and perform noise counting in situations where S/N is large. It is possible to operate a type detection circuit, and therefore has the advantage of having a large dynamic range after detection.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a pulse counting type detection device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of the main parts of the device, and FIG. 3 is a block diagram for explaining the operation of the device. Figure 4 is a block diagram of a conventional pulse count type detection device, Figure 5 is a waveform diagram to explain the operation of the device, and Figure 6 is a characteristic to explain the operation of the device. It is a diagram. 6...Input terminal, 7...Digital type MM, 8...
Level shift circuit, 10...output terminal. Name of agent: Patent attorney Satoshi Nakao and 1 other person!
Figure 2 Figure 3

Claims (1)

[Claims] When performing pulse count demodulation using a digital monostaple multivibrator to obtain a voltage proportional to the frequency deviation of a frequency modulated signal via a limiter circuit, the duty ratio of the monostaple multivibrator is set to 1/2. This is a pulse count type detector that uses a level shift circuit to correct and extract the output offset voltage.