JPS5915411B2 - Keisu Cairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a counting circuit that uses a preset counter and has an upper limit cut function and/or a lower limit cut function of an input frequency.

Generally, in the field of industrial measurement and control, physical quantities, particularly flow rates, etc., are converted into pulse frequencies and transmitted, and the signals are frequency-divided and integrated on the receiving side.

Depending on the characteristics of the transducer, it is often necessary for the counters used in such cases to cut out the low level range, ie not count the low pulse frequency range.

In addition, for the purpose of preventing malfunctions due to noise or other factors, an upper limit may be set for the input pulse frequency so that input pulse frequencies exceeding the upper limit are not counted.

The present invention provides a counting circuit suitable for implementation in such a case, and embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and shows an example of a counting circuit equipped with an input frequency upper limit cut function.

In the figure, VQ is a counter input signal, and this input signal includes a rectangular wave, a trapezoidal wave, a triangular wave, a sine wave, etc.

The PC is a preset counter for which an initial value can be set. For example, MSM153 manufactured by Oki Electric Industry Co., Ltd. is used as this preset counter PC, and the preset input terminals P0, P2, . P
3. P4 and counter output Qt, Q2? Q3tQ4 are interconnected with each other.

By connecting each bit of the output of the preset counter PC and each bit of the corresponding preset input in this way, a preset enable is created.
Even if there is a counter input when the signal arrives, the count will not change.

In other words, the counter input is cut off. Note that IN is an input terminal to which the input signal VQ is applied, PE is a preset enable terminal, and OUT is an output terminal.

R1 and R2 are resistors, D is a diode, and C is a capacitor. These constitute a charging/discharging circuit that receives the input signal VQ of the preset counter PC.

Here, the charging/discharging circuit is configured to have different charging time constants and discharging time constants, and its output is applied to the preset enable terminal PE of the preset counter PC.

FIG. 2 shows waveforms of various parts for explaining the operation of FIG. 1, in which a shows the waveform of the input signal VQ, and b shows the waveform at point Va.

In FIG. 2 1a, the mark indicates the rising edge of the input pulse signal, and in FIG. 2, Vs indicates the threshold level of the preset enable signal.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

First, the preset counter PC is triggered at the rising edge (mark) of the input pulse signal shown in FIG. 2A, and counts the input frequency.

However, if the potential of the preset enable terminal PE is at a high level 11'', the counter is forced to assume the preset input state.

Therefore, if the outputs Q1 to Q4 of the counter itself are applied as the preset input terminals P1 to P4, the counter will maintain the counting state at that point and will not count the input pulses (
Become.

(The capacitor C and resistor R1 shown in FIG.

As shown in Figure 2b, the potential of the preset enable terminal PE at the rising edge of the input pulse is determined by the relationship between the charging/discharging time constant of the charging/discharging circuit consisting of R2 and the diode D and the input pulse period, and it is used as a counter. operation and stop are determined.

This makes it possible to limit the input pulse frequency.

Next, to describe in detail the time constants of the charging/discharging circuit constituted by the capacitor C, resistors R, 1, R2, and diode D, the charging time constant Tc and the discharging time constant TD are Tc-(R, □ and R2 XCTD=R1C (parallel resistance value of
ty cycle) and the threshold level ■s of the preset enable signal.

In this way, it is possible to realize a counting circuit having an input frequency upper limit cutting function in which the upper limit value of the frequency at which the counter input signal is counted is determined by selecting the charging/discharging time constant.

FIG. 3 is a circuit diagram showing another embodiment of the present invention, and shows an example of a counting circuit equipped with a lower limit function of input frequency.

In Fig. 3, the same symbols as in Fig. 1 indicate corresponding parts, and the difference from Fig. 1 is that the counter input signal VQ is applied to the input terminal IN of the preset counter PC, and the inverted signal VQ is applied to the charge/discharge circuit. This is because the diode D is connected in the opposite direction.

Figure 4 shows the waveforms of each part to explain the operation of Figure 3, where a shows the waveform of the input signal VQ, b shows the waveform of the inverted signal Q, and C1 shows the waveform at point Va. This is what is shown.

In FIG. 4A, the mark indicates the rising edge of the input pulse signal, and in FIG. 4C, Vs indicates the threshold level of the preset enable signal.

As is clear from the waveform diagram in FIG. 4, in the embodiment shown in FIG. 3, the input applied to the input terminal IN of the preset counter PC is at a low level of 10.
The count timing is set at the point when the signal changes from "high level to 1", and the relationship between the time constant of the charging/discharging circuit consisting of capacitor C, resistors R1, R2, and diode D and the input pulse period is shown in C in Figure 4. The potential of the preset enable terminal PE at the rising edge of the input pulse is determined so that the counter operation or stop is determined.
This makes it possible to set a lower limit on the input pulse frequency.

And the charging time constant Tc of the charging/discharging circuit composed of capacitor C, resistors R, 1, R2, and diode river
and discharge time constant TD are respectively expressed as Tc = R1C TD = (parallel resistance value of R1 and R2) XC, and the relationship is Tc>TD.

As in the case of FIG. 1, the value is appropriately determined by the frequency to be cut off, the duty cycle of the input pulse, the threshold level Vs of the preset enable signal, etc.

(Thus, by selecting the charging/discharging time constant, the lower limit value of the frequency at which the counter input signal is counted is determined.) A counting circuit equipped with a lower limit cut function of the input frequency can be realized.

FIG. 5 is a circuit diagram showing still another embodiment of the present invention, in which the upper and lower limits of the frequency at which the counter input signal is counted are determined by selecting the charging/discharging time constant. This figure shows an example of a counting circuit that has both functions.

The same parts as in FIGS. 1 and 3 are given the same reference numerals, and their explanation will be omitted.

In Fig. 5, OR is the output of the first charging/discharging circuit consisting of resistor R1゜R2, diode D, and capacitor C, and the output of the second charging/discharging circuit consisting of resistor R1'', R2', diode D', and capacitor C'. The output terminal is connected to the preset enable terminal PE of the preset counter PC.

As mentioned above, this figure 5 has an input frequency upper limit cut function and a lower limit cut function that determine the upper limit value and lower limit value of the counted frequency of the counter input signal, so that the counter input signal VQ and its inverted signal (OR game) for applying the outputs of the first and second charging/discharging circuits to the preset enable terminal PE of the preset counter PC, respectively.
It has been established.

Next, the operation of the embodiment shown in FIG. 5 will be explained.

First, the preset counter PC uses the counter input signal ■Q
Triggered at the rising edge of , the input frequency is counted.

However, the preset enable terminal P inputs the outputs of the first and second charge/discharge circuits via an OR gate.
If the potential of E is high level 1", preset counter P
C is forced into the preset input state.

Therefore, if the outputs Q□-Q4 of the counter itself are applied as the preset input terminals P1-P4, the counter will maintain the counting state at that time and will no longer count input pulses.

Thus, the potential of the preset enable terminal PE at the rising edge of the input pulse is determined by the relationship between the charging/discharging time constant of the first charging/discharging circuit consisting of the capacitor C, resistors R1, R2, and the diode D, and the input pulse period, and the counter The operation/stop of the system is determined.

Counting is not performed in the high frequency region, but counting is performed in the low frequency region, thereby making it possible to limit the input pulse frequency.

Here, the charging time constant TD and discharging time constant TD of the first charging/discharging circuit constituted by the capacitor C, resistors R1, R2, and diode D are respectively Tc=(parallel resistance value of R1 and R2)XC TD2 It is expressed as R1C, with the relationship TC<TD, and its value depends on the frequency to be cut off and the duty cycle (duty cycle) of the input pulse.
ty cycle) and the threshold level of the preset enable signal.

(Thus, by selecting the charging/discharging time constant of this first charging/discharging circuit, the upper limit value of the frequency at which the counter input signal is counted is determined. A counting circuit equipped with an input frequency upper limit cutting function can be realized. .

Next, the counter input signal VQ is input to the preset counter P.
At the same time, the inverted signal v is applied to the input terminal IN of C, and the inverted signal v is applied to a second charging/discharging circuit constituted by a capacitor C', a resistor R1'tB2t, and a diode D' connected in the opposite direction.

Then, the counting timing is taken when the input applied to the input terminal IN of the preset counter PC changes from low level 10" to high level 11", and the capacitor CI, resistors R11', R2', and diode D'
The potential of the preset enable terminal PE at the rising edge of the input pulse is determined by the relationship between the time constant of the second charge/discharge circuit consisting of count and
Counting is not performed in the low frequency region, thereby making it possible to lower the input pulse frequency.

Here, the charging time constant Tc and discharging time constant TD of the second charging/discharging circuit constituted by the capacitor C', resistors R□', R2', and diode D' are Tc = R1, respectively.
'C' TD is expressed as (parallel resistance value of R1' and R2') x C', and the relationship is TC>TD.

As in the case of FIG. 1, the value is appropriately determined by the frequency to be cut off, the duty cycle of the input pulse, the threshold level of the preset enable signal, etc.

Thus, by selecting the charging/discharging time constant of the second charging/discharging circuit, it is possible to realize a counting circuit having a lower limit cutting function of the input frequency, which determines the lower limit of the frequency at which the counter input signal is counted.

In this way, in the embodiment shown in FIG.
It is also possible to have both an upper limit cut function and a lower limit cut function of the input frequency, in which the upper limit and lower limit of the frequency counted by the counter input signal are determined by selecting the charge/discharge time constant of the second charge/discharge circuit.

The present invention has been described above using an example in which the count timing is taken when the input signal applied to the input terminal IN of the preset counter PC changes from low level to high level, but the present invention is not limited to this. Na(,
Conversely, it is also possible to count at the timing when the input of the preset counter PC changes from high level to low level.

Examples thereof are shown in FIGS. 6 and 8.

Figure 6 shows the case of the lower limit, and Figure 8 shows the case of the lower limit.
The figure shows the case of the upper limit.

FIGS. 7 and 9 are explanatory diagrams of the operations in FIGS. 6 and 8, and the marks in the figures indicate the falling points of the input pulses.

FIG. 6 shows that the relationship between the charging time constant and the discharging time constant in a charging/discharging circuit consisting of resistors R, 1, and R2, a diode D, and a capacitor C is the relationship between the discharging time constant and the charging time constant, and FIG. is discharge time constant > charge time constant.

Therefore, the potential of the preset enable terminal PE of the preset counter PC at the falling edge of the input pulse is determined by the relationship between the time constant of the charge/discharge circuit and the input pulse period, and the operation or stop of the counter is determined. Lower and upper frequency limits can be performed.

As is clear from the above description, according to the present invention, the upper and lower limits of the input frequency can be cut without using complicated means (with a simple configuration), so the practical effects are extremely simple. be.

Furthermore, it is extremely effective in that the cost can be reduced due to the simplification of the configuration, and the reliability of the device using the present invention can be improved.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a circuit diagram showing another embodiment of the present invention, FIG. 4 is an explanatory diagram of the operation of FIG. 3, FIGS. 5 and 6,
FIG. 8 is a circuit diagram showing still another embodiment of the present invention;
9 are explanatory views of the operations in FIGS. 6 and 8. PC...Preset counter, R1, R2, R
1'. R2'...Resistor, D, D'...Diode, c, c'...Capacitor.

Claims (1)

[Scope of Claims] 1. A preset counter whose input terminal is supplied with a counter input signal and whose preset input terminal and counter output are connected in phase, and whose input is the counter input signal or its inverted signal and whose output is the preset counter of the preset counter. A charging/discharging circuit is provided in which the voltage is applied to the enable terminal and the charging and discharging time constants are different from each other, and the upper limit or lower limit of the frequency at which the counter input signal is counted is determined by selecting the charging/discharging time constant of the charging/discharging circuit. A counting circuit characterized by having either an upper limit cut function or a lower limit cut function of an input frequency whose value is determined. 2. A preset counter whose input terminal is supplied with a counter input signal and whose preset input terminal and counter output are connected in phase, and a first counter whose input is the counter input signal.
and a second charging/discharging circuit which receives an inverted signal of the counter input signal, and the first and second charging/discharging circuits each have a different charging time constant and a different discharging time constant, and have respective outputs. A charging/discharging circuit section is provided, which applies voltage to a preset enable terminal of the preset counter to serve as a preset enable terminal, and counts counter input signals by selecting charging/discharging time constants of the first and second charging/discharging circuits. A counting circuit characterized in that it has both an upper limit cut function and a lower limit cut function of an input frequency, in which an upper limit value and a lower limit value of the input frequency are determined.