KR920000137A - 불휘발성 반도체기억장치 - Google Patents
불휘발성 반도체기억장치 Download PDFInfo
- Publication number
- KR920000137A KR920000137A KR1019910002613A KR910002613A KR920000137A KR 920000137 A KR920000137 A KR 920000137A KR 1019910002613 A KR1019910002613 A KR 1019910002613A KR 910002613 A KR910002613 A KR 910002613A KR 920000137 A KR920000137 A KR 920000137A
- Authority
- KR
- South Korea
- Prior art keywords
- memory device
- nonvolatile memory
- insulating film
- nonvolatile
- floating gate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims 7
- 230000002093 peripheral effect Effects 0.000 claims 3
- 238000002955 isolation Methods 0.000 claims 1
- 239000011159 matrix material Substances 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Read Only Memory (AREA)
Abstract
Description
Claims (9)
- 제1도전형 반도체기판과, 이 반도체기판의 표면영역에 형성된 제2도전형 불순물영역, 이 불순물영역의 표면영역에 매트릭스형상으로 배치됨과 더불어 기능적으로 블럭을 구성하는 복수개의 불휘발성 기억소자 및, 상기 반도체기판의 표면영역에 형성됨과 더불어 상기 불휘발성 기억소자의 내용의 기록교체동작을 수행하는 경우 상기 불순물영역에 인가되는 전압과 상기 블럭을 구성하는 복수개의 불휘발성 기억소자의 공통소오스 또는 드레인에 인가되는 전압을 각각 제어하는 주변회로(312,1125)를 구비한 것을 특징으로 하는 불휘발성 반도체기억장치.
- 제1항에 있어서, 상기 주변회로(312,1125)는 상기 불휘발성 기억소자의 내용의 소거동작을 수행하는 경우 상기 불순물영역에 인가되는 전압과, 선택되지 않은 블럭의 불휘발성 기억소자의 공통의 소오스 또는 드레인에 인가되는 전압이 선택된 블럭의 불휘발성 기억소자의 공통의 소오스 또는 드레인에 인가되는 전압보다도 낮게 되도록 제어하는 것을 특징으로 하는 불휘발성 반도체기억장치.
- 제1항에 있어서, 상기 불순물영역은 소자분리용 도랑(1101,1303,1401,1501,1601,1704)에 의해 분리되어 있는 것을 특징으로 하는 불휘발성 반도체기억장치.
- 제1항에 있어서, 상기 불휘발성 기억소자의 내용의 소거동작을 수행하는 경우 상기 불순물영역에 인가되는 전압은 외부전원전압과 실질적으로 동등하고, 선택된 블럭의 불휘발성 기억소자의 공통소오스 또는 드레인에 인가되는 전압은 상기 외부전압을 내부승압회로(314,1127 ; 주변회로)에 의해 승압시킨 고전압인 것을 특징으로 하는 불휘발성 반도체기억장치.
- 제1항에 있어서, 상기 불휘발성 반도체소자는 반도체기판상에 터널 전류가 흐르는 제1절연막을 매개하여 배치되는 부유게이트와, 이 부유게이트상에 제2절연막을 매개해서 배치되는 제어게이트를 갖춘 것을 특징으로 하는 불휘발성 반도체기억장치.
- 제1항에 있어서, 상기 불휘발성 반도체소자는 반도체기판상에 제1절연막을 매개해서 배치되는 부유게이트와, 이 부유게이트와 상기 제어게이트의 측벽에 제3절연막을 매개해서 배치되는 한편, 상기 반도체 기관상에 제4절연막을 매개해서 배치되는 선택게이트를 갖춘 것을 특징으로 하는 불휘발성 반도체기억장치.
- 제1항에 있어서, 상기 불휘발성 기억소자는 반도체기판상에 제1절연막을 매개해서 배치되는 부유게이트와, 이 부유게이트상에 제2절연막을 매개해서 배치됨과 더불어 일부가 상기 부유게이트에 의해 덮여지지 않은 채널영역상에 제3절연막을 매개해서 배치되는 제어게이트를 구비한 것을 특징으로 하는 불휘발성 반도체기억장치.
- 제1항에 있어서, 상기 불휘발성 기억소자는 반도체기판상에 제1절연막을 매개해서 배치되는 부유게이트와, 이 부유게이트상에 제2절연막을 매개해서 배치되는 제어게이트로 이루어진 기억소자가 복수개 직렬로 접속되어 기본단위를 구성하고 있는 것을 특징으로 하는 불휘발성 반도체기억장치.
- 제1항에 있어서, 상기 반도체기판은 n형 실리콘기판이고, 상기 불순물영역은 p형 웰인 것을 특징으로 하는 불휘발성 반도체기억장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2-40911 | 1990-02-23 | ||
JP2040911A JP2504599B2 (ja) | 1990-02-23 | 1990-02-23 | 不揮発性半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR920000137A true KR920000137A (ko) | 1992-01-10 |
KR940005899B1 KR940005899B1 (ko) | 1994-06-24 |
Family
ID=12593689
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910002613A KR940005899B1 (ko) | 1990-02-23 | 1991-02-19 | 불휘발성 반도체기억장치 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5262985A (ko) |
EP (1) | EP0443610B1 (ko) |
JP (1) | JP2504599B2 (ko) |
KR (1) | KR940005899B1 (ko) |
DE (1) | DE69125875T2 (ko) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR930007527B1 (ko) * | 1990-09-22 | 1993-08-12 | 삼성전자 주식회사 | 스토리지 셀 어레이와 주변회로를 갖는 불휘발성 반도체 메모리 장치의 제조방법 및 그 구조 |
JP2799530B2 (ja) * | 1991-11-16 | 1998-09-17 | 三菱電機株式会社 | 半導体記憶装置の製造方法 |
EP1126474B1 (en) * | 1991-11-20 | 2003-03-05 | Fujitsu Limited | Semiconductor memory device |
DE69227020T2 (de) * | 1992-03-11 | 1999-02-18 | Stmicroelectronics S.R.L., Agrate Brianza, Mailand/Milano | Dekodierschaltung fähig zur Ubertragung von positiven und negativen Spannungen |
US5411908A (en) * | 1992-05-28 | 1995-05-02 | Texas Instruments Incorporated | Flash EEPROM array with P-tank insulated from substrate by deep N-tank |
WO1994014196A1 (en) * | 1992-12-08 | 1994-06-23 | National Semiconductor Corporation | High density contactless flash eprom array using channel erase |
JPH07161845A (ja) * | 1993-12-02 | 1995-06-23 | Nec Corp | 半導体不揮発性記憶装置 |
US5432749A (en) * | 1994-04-26 | 1995-07-11 | National Semiconductor Corporation | Non-volatile memory cell having hole confinement layer for reducing band-to-band tunneling |
US5687118A (en) * | 1995-11-14 | 1997-11-11 | Programmable Microelectronics Corporation | PMOS memory cell with hot electron injection programming and tunnelling erasing |
US5867425A (en) * | 1997-04-11 | 1999-02-02 | Wong; Ting-Wah | Nonvolatile memory capable of using substrate hot electron injection |
US5896315A (en) * | 1997-04-11 | 1999-04-20 | Programmable Silicon Solutions | Nonvolatile memory |
JP4427108B2 (ja) * | 1998-03-27 | 2010-03-03 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP2000311992A (ja) * | 1999-04-26 | 2000-11-07 | Toshiba Corp | 不揮発性半導体記憶装置およびその製造方法 |
US6831325B2 (en) * | 2002-12-20 | 2004-12-14 | Atmel Corporation | Multi-level memory cell with lateral floating spacers |
KR20050009104A (ko) * | 2003-07-15 | 2005-01-24 | 현대자동차주식회사 | 파워스티어링 펌프의 결합구조 |
US8099783B2 (en) * | 2005-05-06 | 2012-01-17 | Atmel Corporation | Security method for data protection |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2645585B2 (ja) * | 1989-03-10 | 1997-08-25 | 工業技術院長 | 半導体不揮発性メモリ及びその書き込み方法 |
JPS62183161A (ja) * | 1986-02-07 | 1987-08-11 | Hitachi Ltd | 半導体集積回路装置 |
JPS6352478A (ja) * | 1986-08-22 | 1988-03-05 | Hitachi Ltd | 半導体集積回路装置 |
JPS63211767A (ja) * | 1987-02-27 | 1988-09-02 | Toshiba Corp | 半導体記憶装置 |
JPH0814991B2 (ja) * | 1988-01-28 | 1996-02-14 | 株式会社東芝 | 電気的消去可能不揮発性半導体記憶装置 |
US5075890A (en) * | 1989-05-02 | 1991-12-24 | Kabushiki Kaisha Toshiba | Electrically erasable programmable read-only memory with nand cell |
US5029139A (en) * | 1989-07-19 | 1991-07-02 | Texas Instruments Incorporated | Word erasable buried bit line EEPROM |
US5126808A (en) * | 1989-10-23 | 1992-06-30 | Advanced Micro Devices, Inc. | Flash EEPROM array with paged erase architecture |
US5132935A (en) * | 1990-04-16 | 1992-07-21 | Ashmore Jr Benjamin H | Erasure of eeprom memory arrays to prevent over-erased cells |
US5138576A (en) * | 1991-11-06 | 1992-08-11 | Altera Corporation | Method and apparatus for erasing an array of electrically erasable EPROM cells |
-
1990
- 1990-02-23 JP JP2040911A patent/JP2504599B2/ja not_active Expired - Lifetime
-
1991
- 1991-02-19 KR KR1019910002613A patent/KR940005899B1/ko not_active IP Right Cessation
- 1991-02-22 US US07/659,183 patent/US5262985A/en not_active Expired - Lifetime
- 1991-02-22 DE DE69125875T patent/DE69125875T2/de not_active Expired - Fee Related
- 1991-02-22 EP EP91102635A patent/EP0443610B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2504599B2 (ja) | 1996-06-05 |
DE69125875D1 (de) | 1997-06-05 |
EP0443610A2 (en) | 1991-08-28 |
JPH03245566A (ja) | 1991-11-01 |
US5262985A (en) | 1993-11-16 |
KR940005899B1 (ko) | 1994-06-24 |
DE69125875T2 (de) | 1997-09-25 |
EP0443610A3 (en) | 1994-10-05 |
EP0443610B1 (en) | 1997-05-02 |
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