KR900007135B1 - 우선 선택회로를 갖는 바퍼 스토리지 제어 시스템 - Google Patents
우선 선택회로를 갖는 바퍼 스토리지 제어 시스템 Download PDFInfo
- Publication number
- KR900007135B1 KR900007135B1 KR1019860008884A KR860008884A KR900007135B1 KR 900007135 B1 KR900007135 B1 KR 900007135B1 KR 1019860008884 A KR1019860008884 A KR 1019860008884A KR 860008884 A KR860008884 A KR 860008884A KR 900007135 B1 KR900007135 B1 KR 900007135B1
- Authority
- KR
- South Korea
- Prior art keywords
- data
- buffer storage
- request
- bypass
- priority selection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0855—Overlapped cache accessing, e.g. pipeline
- G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
Claims (3)
- 주기억장치(10)의 내용의 일부를 기억하기 위한 버퍼 스토리지(30)를 갖는 중앙처리장치(100)를 갖는 시스템으로서 주기억장치로부터 버퍼 스토리지로 블록 전송이 실행될 때, 처리되어야 할 데이타가 직접 연산 유니트(50)로 또는 명령 처리 유니트(40)로 바이패스 동작에 의해서 전송되고, 상기 전숭된 데이타가 상기 버퍼 스토리지(30)에 기입되고, 상기·버퍼 스토리지로 1블록의 모든 데이타가 기입되지 않았을 때 상기버퍼 스토리지에 기입된 부분만 독출할 수 있고, 상기 바이패스 동작과 관련된 데이타와 상기 바이패스 동작에 관련된 상기 데이타에 뒤이어 상기 주기억장치(10)로부터 전송된 데이타에 대하여 바이패스 동작 종료시각으로부터 상기 버퍼 스토리지로의 기입동작의 종료시각까지의 동안에 후속 억세스 요청에 따르는 상기버퍼 스토리지로의 억세스가 금지되는 양상으로 동작하는 것이 특징인 우선 선택회로를 갖는 버퍼 스토리지 제어 시스탬.
- 제 1항에서, 우선 선택 바이패스 사이클 종료시각으로부터 제l회째의 우선 선택 무브-인 사이를 종료시각까지의 동안에 우선 선택 금지신호가 "1" 로 세트되는 것이 특징인 우선 선택 회로를 갖는 버퍼 스토리지 제어 시스템.
- 제2항에서, 바이패스 요청 데이타에 우선 선택이 주어지고, 아직 우선 선택이 주어지지 않은 요청데이타가 상기 기간중에 연속적으로 나타날 때에만 우선 선택 금지 신호가 " 1"로 되는 것이 특징인 우선 선택 회로를 갖는 버퍼 스토리지 제어 시스템.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60241799A JPS62102344A (ja) | 1985-10-29 | 1985-10-29 | バツフア・メモリ制御方式 |
JP60-241799 | 1985-10-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR870004370A KR870004370A (ko) | 1987-05-09 |
KR900007135B1 true KR900007135B1 (ko) | 1990-09-29 |
Family
ID=17079682
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019860008884A Expired KR900007135B1 (ko) | 1985-10-29 | 1986-10-23 | 우선 선택회로를 갖는 바퍼 스토리지 제어 시스템 |
Country Status (9)
Country | Link |
---|---|
US (1) | US4800490A (ko) |
EP (1) | EP0220990B1 (ko) |
JP (1) | JPS62102344A (ko) |
KR (1) | KR900007135B1 (ko) |
AU (1) | AU575261B2 (ko) |
BR (1) | BR8605264A (ko) |
CA (1) | CA1279407C (ko) |
DE (1) | DE3678789D1 (ko) |
ES (1) | ES2020943B3 (ko) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6297036A (ja) * | 1985-07-31 | 1987-05-06 | テキサス インスツルメンツ インコ−ポレイテツド | 計算機システム |
JP2714952B2 (ja) * | 1988-04-20 | 1998-02-16 | 株式会社日立製作所 | 計算機システム |
EP0348628A3 (en) * | 1988-06-28 | 1991-01-02 | International Business Machines Corporation | Cache storage system |
US5073969A (en) * | 1988-08-01 | 1991-12-17 | Intel Corporation | Microprocessor bus interface unit which changes scheduled data transfer indications upon sensing change in enable signals before receiving ready signal |
US5125083A (en) * | 1989-02-03 | 1992-06-23 | Digital Equipment Corporation | Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system |
US5247639A (en) * | 1989-06-20 | 1993-09-21 | Nec Corporation | Microprocessor having cache bypass signal terminal |
US5255377A (en) * | 1989-11-13 | 1993-10-19 | Intel Corporation | Interface for arbitrating access to the paging unit of a computer processor |
US5224214A (en) * | 1990-04-12 | 1993-06-29 | Digital Equipment Corp. | BuIffet for gathering write requests and resolving read conflicts by matching read and write requests |
US5333267A (en) * | 1990-05-29 | 1994-07-26 | Apple Computer, Inc. | Ring interconnect system architecture |
JP3481425B2 (ja) * | 1997-06-16 | 2003-12-22 | エヌイーシーコンピュータテクノ株式会社 | キャッシュ装置 |
WO2011010184A1 (en) * | 2009-07-20 | 2011-01-27 | Freescale Semiconductor, Inc. | Signal processing system, integrated circuit comprising buffer control logic and method therefor |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4042911A (en) * | 1976-04-30 | 1977-08-16 | International Business Machines Corporation | Outer and asynchronous storage extension system |
JPS601655B2 (ja) * | 1977-11-30 | 1985-01-16 | 株式会社東芝 | デ−タプリフェツチ方式 |
US4189770A (en) * | 1978-03-16 | 1980-02-19 | International Business Machines Corporation | Cache bypass control for operand fetches |
JPS5697146A (en) * | 1979-12-29 | 1981-08-05 | Fujitsu Ltd | Instruction fetch control system |
JPS57105879A (en) * | 1980-12-23 | 1982-07-01 | Hitachi Ltd | Control system for storage device |
US4500954A (en) * | 1981-10-15 | 1985-02-19 | International Business Machines Corporation | Cache bypass system with post-block transfer directory examinations for updating cache and/or maintaining bypass |
JPS59180878A (ja) * | 1983-03-31 | 1984-10-15 | Fujitsu Ltd | バツフアストア制御方式 |
-
1985
- 1985-10-29 JP JP60241799A patent/JPS62102344A/ja active Granted
-
1986
- 1986-10-20 CA CA000520897A patent/CA1279407C/en not_active Expired - Lifetime
- 1986-10-23 KR KR1019860008884A patent/KR900007135B1/ko not_active Expired
- 1986-10-23 EP EP86402373A patent/EP0220990B1/en not_active Expired - Lifetime
- 1986-10-23 DE DE8686402373T patent/DE3678789D1/de not_active Expired - Lifetime
- 1986-10-23 ES ES86402373T patent/ES2020943B3/es not_active Expired - Lifetime
- 1986-10-24 AU AU64436/86A patent/AU575261B2/en not_active Ceased
- 1986-10-28 BR BR8605264A patent/BR8605264A/pt not_active IP Right Cessation
- 1986-10-29 US US06/924,329 patent/US4800490A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
ES2020943B3 (es) | 1991-10-16 |
BR8605264A (pt) | 1987-07-28 |
KR870004370A (ko) | 1987-05-09 |
EP0220990B1 (en) | 1991-04-17 |
US4800490A (en) | 1989-01-24 |
CA1279407C (en) | 1991-01-22 |
AU6443686A (en) | 1987-04-30 |
EP0220990A3 (en) | 1988-07-27 |
JPH0410102B2 (ko) | 1992-02-24 |
DE3678789D1 (de) | 1991-05-23 |
JPS62102344A (ja) | 1987-05-12 |
EP0220990A2 (en) | 1987-05-06 |
AU575261B2 (en) | 1988-07-21 |
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