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KR870004370A - 우선 선택회로를 갖는 바퍼 스토리지 제어 시스템 - Google Patents

우선 선택회로를 갖는 바퍼 스토리지 제어 시스템

Info

Publication number
KR870004370A
KR870004370A KR1019860008884A KR860008884A KR870004370A KR 870004370 A KR870004370 A KR 870004370A KR 1019860008884 A KR1019860008884 A KR 1019860008884A KR 860008884 A KR860008884 A KR 860008884A KR 870004370 A KR870004370 A KR 870004370A
Authority
KR
South Korea
Prior art keywords
control system
selection circuit
storage control
buffer storage
buffer
Prior art date
Application number
KR1019860008884A
Other languages
English (en)
Other versions
KR900007135B1 (ko
Inventor
쯔도무 다나까
유지 오이나가
Original Assignee
후지쓰 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 후지쓰 가부시끼가이샤 filed Critical 후지쓰 가부시끼가이샤
Publication of KR870004370A publication Critical patent/KR870004370A/ko
Application granted granted Critical
Publication of KR900007135B1 publication Critical patent/KR900007135B1/ko

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855Overlapped cache accessing, e.g. pipeline
    • G06F12/0859Overlapped cache accessing, e.g. pipeline with reload from main memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1019860008884A 1985-10-29 1986-10-23 우선 선택회로를 갖는 바퍼 스토리지 제어 시스템 KR900007135B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60241799A JPS62102344A (ja) 1985-10-29 1985-10-29 バツフア・メモリ制御方式
JP60-241799 1985-10-29

Publications (2)

Publication Number Publication Date
KR870004370A true KR870004370A (ko) 1987-05-09
KR900007135B1 KR900007135B1 (ko) 1990-09-29

Family

ID=17079682

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860008884A KR900007135B1 (ko) 1985-10-29 1986-10-23 우선 선택회로를 갖는 바퍼 스토리지 제어 시스템

Country Status (9)

Country Link
US (1) US4800490A (ko)
EP (1) EP0220990B1 (ko)
JP (1) JPS62102344A (ko)
KR (1) KR900007135B1 (ko)
AU (1) AU575261B2 (ko)
BR (1) BR8605264A (ko)
CA (1) CA1279407C (ko)
DE (1) DE3678789D1 (ko)
ES (1) ES2020943B3 (ko)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6297036A (ja) * 1985-07-31 1987-05-06 テキサス インスツルメンツ インコ−ポレイテツド 計算機システム
JP2714952B2 (ja) * 1988-04-20 1998-02-16 株式会社日立製作所 計算機システム
EP0348628A3 (en) * 1988-06-28 1991-01-02 International Business Machines Corporation Cache storage system
US5073969A (en) * 1988-08-01 1991-12-17 Intel Corporation Microprocessor bus interface unit which changes scheduled data transfer indications upon sensing change in enable signals before receiving ready signal
US5125083A (en) * 1989-02-03 1992-06-23 Digital Equipment Corporation Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system
US5247639A (en) * 1989-06-20 1993-09-21 Nec Corporation Microprocessor having cache bypass signal terminal
US5255377A (en) * 1989-11-13 1993-10-19 Intel Corporation Interface for arbitrating access to the paging unit of a computer processor
US5224214A (en) * 1990-04-12 1993-06-29 Digital Equipment Corp. BuIffet for gathering write requests and resolving read conflicts by matching read and write requests
US5333267A (en) * 1990-05-29 1994-07-26 Apple Computer, Inc. Ring interconnect system architecture
JP3481425B2 (ja) * 1997-06-16 2003-12-22 エヌイーシーコンピュータテクノ株式会社 キャッシュ装置
EP2457168B1 (en) 2009-07-20 2018-09-26 NXP USA, Inc. Signal processing system, integrated circuit comprising buffer control logic and method therefor

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4042911A (en) * 1976-04-30 1977-08-16 International Business Machines Corporation Outer and asynchronous storage extension system
JPS601655B2 (ja) * 1977-11-30 1985-01-16 株式会社東芝 デ−タプリフェツチ方式
US4189770A (en) * 1978-03-16 1980-02-19 International Business Machines Corporation Cache bypass control for operand fetches
JPS5697146A (en) * 1979-12-29 1981-08-05 Fujitsu Ltd Instruction fetch control system
JPS57105879A (en) * 1980-12-23 1982-07-01 Hitachi Ltd Control system for storage device
US4500954A (en) * 1981-10-15 1985-02-19 International Business Machines Corporation Cache bypass system with post-block transfer directory examinations for updating cache and/or maintaining bypass
JPS59180878A (ja) * 1983-03-31 1984-10-15 Fujitsu Ltd バツフアストア制御方式

Also Published As

Publication number Publication date
AU6443686A (en) 1987-04-30
AU575261B2 (en) 1988-07-21
JPS62102344A (ja) 1987-05-12
BR8605264A (pt) 1987-07-28
JPH0410102B2 (ko) 1992-02-24
EP0220990A2 (en) 1987-05-06
KR900007135B1 (ko) 1990-09-29
ES2020943B3 (es) 1991-10-16
CA1279407C (en) 1991-01-22
EP0220990B1 (en) 1991-04-17
US4800490A (en) 1989-01-24
EP0220990A3 (en) 1988-07-27
DE3678789D1 (de) 1991-05-23

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