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KR900005301A - Synchronous Serial / Parallel Data Conversion Circuit - Google Patents

Synchronous Serial / Parallel Data Conversion Circuit Download PDF

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Publication number
KR900005301A
KR900005301A KR1019880012693A KR880012693A KR900005301A KR 900005301 A KR900005301 A KR 900005301A KR 1019880012693 A KR1019880012693 A KR 1019880012693A KR 880012693 A KR880012693 A KR 880012693A KR 900005301 A KR900005301 A KR 900005301A
Authority
KR
South Korea
Prior art keywords
conversion circuit
data conversion
parallel data
synchronous serial
data
Prior art date
Application number
KR1019880012693A
Other languages
Korean (ko)
Inventor
김진욱
Original Assignee
최근선
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 최근선, 주식회사 금성사 filed Critical 최근선
Priority to KR1019880012693A priority Critical patent/KR900005301A/en
Publication of KR900005301A publication Critical patent/KR900005301A/en

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  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)

Abstract

내용 없음No content

Description

싱크로노스 직렬/병렬 데이타 변환 회로Synchronous Serial / Parallel Data Conversion Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 싱크로노스 직.병렬 데이타 변환 회로의 블럭도.1 is a block diagram of a synchronic serial-parallel data conversion circuit according to the present invention.

제2도는 본 발명에 따른 싱크로노스 직.병렬 데이타 변환 회로도.2 is a schematic diagram of a synchronic serial / parallel data conversion circuit according to the present invention.

Claims (1)

데이타 직/병렬 변환 회로에 있어서, 데이타 출력 장치로서 쉬프트 레지스타 1(2)와 페리티 발생기(1) 및 Tx 데이타 콘트롤부(3)와 싱크 클락펄스 발생부(5)와 비스카운터(4)로 구성된 송신부를 포함하고 데이타 입력장치로서 쉬프트 레지스타2(2)와 페리티 검출기(7)와 비스카운트(8) 및 Px 신호 발생부(9)로 구성된 수신부를 포함하여 싱크 클락 펄스에 의해 송.수신이 더욱 신속하고 정확한 것을 특징으로 하는 싱크로노스 직/병렬 데이타 변환회로.In the data serial / parallel conversion circuit, a shift register 1 (2), a parity generator (1), a Tx data controller (3), a sink clock pulse generator (5), and a non-counter (4) as data output devices. It includes a transmitter configured as a data input device and includes a receiver configured as a shift register 2 (2), a parity detector (7), a non-counter (8), and a Px signal generator (9). Synchronous serial / parallel data conversion circuit, characterized in that the reception is faster and more accurate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880012693A 1988-09-30 1988-09-30 Synchronous Serial / Parallel Data Conversion Circuit KR900005301A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019880012693A KR900005301A (en) 1988-09-30 1988-09-30 Synchronous Serial / Parallel Data Conversion Circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880012693A KR900005301A (en) 1988-09-30 1988-09-30 Synchronous Serial / Parallel Data Conversion Circuit

Publications (1)

Publication Number Publication Date
KR900005301A true KR900005301A (en) 1990-04-13

Family

ID=68158293

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880012693A KR900005301A (en) 1988-09-30 1988-09-30 Synchronous Serial / Parallel Data Conversion Circuit

Country Status (1)

Country Link
KR (1) KR900005301A (en)

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