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KR900001150A - PCM data generation circuit - Google Patents

PCM data generation circuit Download PDF

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Publication number
KR900001150A
KR900001150A KR1019880008014A KR880008014A KR900001150A KR 900001150 A KR900001150 A KR 900001150A KR 1019880008014 A KR1019880008014 A KR 1019880008014A KR 880008014 A KR880008014 A KR 880008014A KR 900001150 A KR900001150 A KR 900001150A
Authority
KR
South Korea
Prior art keywords
channel
data
pcm
counter
frame sync
Prior art date
Application number
KR1019880008014A
Other languages
Korean (ko)
Other versions
KR910008754B1 (en
Inventor
류광희
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019880008014A priority Critical patent/KR910008754B1/en
Publication of KR900001150A publication Critical patent/KR900001150A/en
Application granted granted Critical
Publication of KR910008754B1 publication Critical patent/KR910008754B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B14/00—Transmission systems not characterised by the medium used for transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B14/00—Transmission systems not characterised by the medium used for transmission
    • H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

내용 없음No content

Description

PCM데이타 발생회로PCM data generation circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 블럭도,1 is a block diagram according to the present invention,

제2도는 본 발명에 따른 제1도의 구체회로도,2 is a detailed circuit diagram of FIG. 1 according to the present invention;

제3도는 본 발명에 따른 제2도의 동작파형도.3 is an operational waveform diagram of FIG. 2 according to the present invention;

Claims (1)

음성신호의 샘플링 주기를 갖는 프레임싱크 신호와, 상기 프레임싱크 기간내의 전송시 공급하는 비트타임클럭신호와 채널 데이타와 비트타임의 기준클럭 신호를 받아 PCM데이타를 발생하는 회로에 있어서, PCM의 기본 펄스인 상기 프레임싱크 신호를 입력신호로 하여 카운트하여 소정 래치하여 PCM기본 데이타를 발생하는 카운터부(100)와, 상기 카운터부(100)의 카운트된 출력을 입력 데이타로 하여 A-law 및 μ-law방식의 선택에 따라 해당 PCM데이타를 발생하는 쉬프트레지스터부(200)와, 상기 프레임 싱크 및 비트타임 클럭에 따라 채널선택에 필요한 신호공급하는 채널 카운터부(300)와, 상기 채널 카운터부(300)에서 출력된 데이타와 주어진 채널 데이타 유효기간만 발생하는 비트 타임클럭에 의해 주어진 채널값을 얻은 후 상기 채널 카운터부(300)의 출력과 비교하여 상기 쉬프트레지스터부(200)에 주어진 채널 위치를 알려주는 채널 선택부(400)으로 구성됨을 특징으로 하는 PCM데이타 발생회로.A basic pulse of a PCM in a circuit for generating PCM data by receiving a frame sync signal having a sampling period of an audio signal, a bit time clock signal supplied during transmission within the frame sync period, a channel data, and a reference clock signal of bit time. A-law and [mu] -law using the counter 100 for counting the frame sync signal as an input signal and predetermined latching to generate PCM basic data, and the counted output of the counter 100 as input data. A shift register unit 200 for generating corresponding PCM data according to a selection of a scheme, a channel counter unit 300 for supplying signals necessary for channel selection according to the frame sync and bit time clocks, and the channel counter unit 300 After obtaining the channel value given by the bit time clock that generates only the data outputted from the data and the given channel data validity period, the output of the channel counter 300 The PCM data generating circuit in the shift register 200 is characterized by a composed of a channel selection unit 400 indicating a given channel position. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880008014A 1988-06-30 1988-06-30 PCM data generation circuit KR910008754B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019880008014A KR910008754B1 (en) 1988-06-30 1988-06-30 PCM data generation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880008014A KR910008754B1 (en) 1988-06-30 1988-06-30 PCM data generation circuit

Publications (2)

Publication Number Publication Date
KR900001150A true KR900001150A (en) 1990-01-31
KR910008754B1 KR910008754B1 (en) 1991-10-19

Family

ID=19275706

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880008014A KR910008754B1 (en) 1988-06-30 1988-06-30 PCM data generation circuit

Country Status (1)

Country Link
KR (1) KR910008754B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100298289B1 (en) * 1998-12-24 2001-10-26 서평원 Voice Inverter of Voice Mail System

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100298289B1 (en) * 1998-12-24 2001-10-26 서평원 Voice Inverter of Voice Mail System

Also Published As

Publication number Publication date
KR910008754B1 (en) 1991-10-19

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