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KR900003725A - 테스트 모우드 기능 수행 입력 회로 - Google Patents

테스트 모우드 기능 수행 입력 회로 Download PDF

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Publication number
KR900003725A
KR900003725A KR1019880011062A KR880011062A KR900003725A KR 900003725 A KR900003725 A KR 900003725A KR 1019880011062 A KR1019880011062 A KR 1019880011062A KR 880011062 A KR880011062 A KR 880011062A KR 900003725 A KR900003725 A KR 900003725A
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KR
South Korea
Prior art keywords
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inverter
input
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transmission
Prior art date
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Application number
KR1019880011062A
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English (en)
Other versions
KR950011803B1 (ko
Inventor
김학근
Original Assignee
이만용
금성반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이만용, 금성반도체 주식회사 filed Critical 이만용
Priority to KR1019880011062A priority Critical patent/KR950011803B1/ko
Priority to GB8919372A priority patent/GB2222689A/en
Priority to DE3928559A priority patent/DE3928559A1/de
Priority to JP1224315A priority patent/JPH02162273A/ja
Publication of KR900003725A publication Critical patent/KR900003725A/ko
Application granted granted Critical
Publication of KR950011803B1 publication Critical patent/KR950011803B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318522—Test of Sequential circuits
    • G01R31/318527—Test of counters

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

내용 없음

Description

테스트 모우드 기능 수행 입력 회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 따른 테스트 모우드 기능 수행 입력 회로도.
제3도는 본 발명의 입력 회로의 적용예.
제4도는 본 발명에 따른 파형 설명도.

Claims (1)

  1. 크록 입력단에 인버터(2)를 거쳐 낸드게이트(4)를 거치고 토글 플립플롭(6)(8)(10)(12)(14)(16)를 거치고 낸드게이트(18)(20)을 통하고 토글 플립플롭(29)(31)을 연속 통하여 각각 출력단(Q7B)와 (Q8B)에 출력되고 테스트 입력단(22)이 인버터(23)를 거쳐 낸드게이트(18)에 연결되고 인버터(2)의 출력이 인버터(25)를 거치고 낸드게이트(27)을 통해 인버터(28)에 인가되고 입력 A단(33)이 낸드게이트(34)(36)을 통해 INA에 인가되는 테스트 모우드 기능 수행 입력 회로에 있어서, 입력 A단(40)이 테스트단(40)과 공통 결합되고 그 신호가 트랜스미션게이트(102)를 거쳐 트랜스미션게이트(103)과 트랜스미션게이트(105)의 소오스단을 거쳐 공통게이트단을 통해 트랜스미션게이트(105)의 드레인단에 연결되고 트랜스미션게이트(107)을 거쳐 그 드레인이 VDD단과 그 게이트가 VSS단에 접속되고 트랜스미션게이트(108)(109)의 인버터(150)와 트랜스미션게이트(110)(111)의 인버터(151)을 거치고 낸드게이트(18)의 입력단에 연결되고 인버터(150)의 출력이 낸드게이트(27)의 입력단에 연결되어 구성된 것을 특징으로 하는 테스트 모우드 기능 수행 입력 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880011062A 1988-08-30 1988-08-30 테스트 모우드 기능 수행, 입력 회로 Expired - Fee Related KR950011803B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019880011062A KR950011803B1 (ko) 1988-08-30 1988-08-30 테스트 모우드 기능 수행, 입력 회로
GB8919372A GB2222689A (en) 1988-08-30 1989-08-25 Testing logic circuits
DE3928559A DE3928559A1 (de) 1988-08-30 1989-08-29 Eingangsschaltung zur durchfuehrung von pruefbetriebsarten
JP1224315A JPH02162273A (ja) 1988-08-30 1989-08-30 テストモード機能遂行入力回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880011062A KR950011803B1 (ko) 1988-08-30 1988-08-30 테스트 모우드 기능 수행, 입력 회로

Publications (2)

Publication Number Publication Date
KR900003725A true KR900003725A (ko) 1990-03-26
KR950011803B1 KR950011803B1 (ko) 1995-10-10

Family

ID=19277257

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880011062A Expired - Fee Related KR950011803B1 (ko) 1988-08-30 1988-08-30 테스트 모우드 기능 수행, 입력 회로

Country Status (4)

Country Link
JP (1) JPH02162273A (ko)
KR (1) KR950011803B1 (ko)
DE (1) DE3928559A1 (ko)
GB (1) GB2222689A (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200134773A (ko) * 2019-05-23 2020-12-02 우경제 곤약 떡 제조 방법

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5300011B2 (ja) * 2009-02-04 2013-09-25 ローム株式会社 半導体装置
US8829932B2 (en) * 2010-07-23 2014-09-09 Fairchild Semiconductor Corporation No pin test mode

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2917126C2 (de) * 1979-04-27 1983-01-27 Philips Patentverwaltung Gmbh, 2000 Hamburg Verfahren zum Prüfen einer integrierten Schaltung und Anordnung zur Durchführung des Verfahrens
JPS57133656A (en) * 1981-02-12 1982-08-18 Nec Corp Semiconductor integrated circuit incorporated with test circuit
JPS6040870B2 (ja) * 1982-08-10 1985-09-12 松下電工株式会社 電気かみそりの外刃
JPS62170094A (ja) * 1986-01-21 1987-07-27 Mitsubishi Electric Corp 半導体記憶回路
US4733168A (en) * 1986-03-21 1988-03-22 Harris Corporation Test enabling circuit for enabling overhead test circuitry in programmable devices
JP2721151B2 (ja) * 1986-04-01 1998-03-04 株式会社東芝 半導体集積回路装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200134773A (ko) * 2019-05-23 2020-12-02 우경제 곤약 떡 제조 방법

Also Published As

Publication number Publication date
DE3928559A1 (de) 1990-04-05
GB2222689A (en) 1990-03-14
JPH02162273A (ja) 1990-06-21
KR950011803B1 (ko) 1995-10-10
GB8919372D0 (en) 1989-10-11

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