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KR890013862A - 전압레벨 변환회로 - Google Patents

전압레벨 변환회로 Download PDF

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Publication number
KR890013862A
KR890013862A KR1019890002089A KR890002089A KR890013862A KR 890013862 A KR890013862 A KR 890013862A KR 1019890002089 A KR1019890002089 A KR 1019890002089A KR 890002089 A KR890002089 A KR 890002089A KR 890013862 A KR890013862 A KR 890013862A
Authority
KR
South Korea
Prior art keywords
voltage level
signal
pull
input
converting circuit
Prior art date
Application number
KR1019890002089A
Other languages
English (en)
Other versions
KR910009077B1 (ko
Inventor
스미오 다나카
시게루 아츠미
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR890013862A publication Critical patent/KR890013862A/ko
Application granted granted Critical
Publication of KR910009077B1 publication Critical patent/KR910009077B1/ko

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/10—Arrangements incorporating converting means for enabling loads to be operated at will from different kinds of power supplies, e.g. from AC or DC
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Read Only Memory (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

내용 없음.

Description

전압레벨 변환회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 통상적인 EPROM의 구성을 도시한 회로도,
제4도는 본 발명의 실시예에 따른 전압레벨 변환회로의 회로도이다.

Claims (6)

  1. 제1전압레벨의 “1”레벨 입력논리 신호나 “0”레벨 입력논리신호를 받아들여서 상기 제1전압레벨보다 높은 제2전압레벨의 “1”레벨 출력논리 신호나 “0”레벨 출력 논리신호를 출력하는 전압레벨 변환회로에 있어서, 입력신호를 공급받아 전송받는 게이트수단과, 이 게이트수단으로부터 입력신호를 공급받아 대응되는 출력신호를 출력하며 상기 제2전압레벨의 전압에 의해 바이어스되어 있는 인버터수단, 이 인버터수단에 대한 입력신호의 전압레벨을 올리기 위해 “0”출력신호에 응답하여 동작하는 풀-엎수단 및, 출력신호의 전압레벨을 낮추기 위해 “1”입력신호에 응답하여 동작하는 풀-다운 수단으로 구성된 것을 특징으로하는 전압레벨 변환회로.
  2. 제1항에 있어서, 상기 인버터 수단이 입력신호를 공급받아 입력단자와 추력신호를 출력하는 출력간자를 갖춘 CMOS인버터 회로(46,47)로 구성된 것을 특징으로하는 전압레벨 변환회로.
  3. 제1항에 있어서, 상기 게이트수단은 전압레벨 변환회로의 입력단과 CMOS인버터회로(46,47)의 입력단간에 소오스 및 드레인 통로가 직렬로 접속된 제1 및 제2MOS트랜지스터(42,43)로 구성된 것을 특징으로하는 전압레벨 변환회로.
  4. 제1항에 있어서, 상기 풀-업 수단은 추력신호가 공급되는 게이트전극을 갖춘 제2도전형 MOS트랜지스터(45)를 구비하여 구성되고, 상기 풀-다운 수단은 입력신호가 공급되는 게이트전극을 갖춘 제1도전형 MOS트랜지스터(48)를 구비하여 구성된 것을 특징으로 전압레벨 변환회로.
  5. 제4항에 있어서, 상기 풀-업수단은 CMOS인버터회로(46,47)의 입력을 제1전압레벨에 결합시키기 위한 캐패시터(44)를 구비하여 구성된 것을 특징으로하는 전압레벨 변환회로.
  6. 제4항에 있어서, 상기 풀-다운 수단은 CMOS인버터회로(46,47)의 출력을 접지레벨을 결합시키기 위한 캐패시터(49)를 구비하여 구성된 것을 특징으로 하는 전압레벨 변환회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890002089A 1988-02-22 1989-02-22 전압레벨 변환회로 KR910009077B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3929488A JP2585348B2 (ja) 1988-02-22 1988-02-22 不揮発性半導体記憶装置
JP63-39294 1988-02-22

Publications (2)

Publication Number Publication Date
KR890013862A true KR890013862A (ko) 1989-09-26
KR910009077B1 KR910009077B1 (ko) 1991-10-28

Family

ID=12549122

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890002089A KR910009077B1 (ko) 1988-02-22 1989-02-22 전압레벨 변환회로

Country Status (3)

Country Link
US (1) US4926070A (ko)
JP (1) JP2585348B2 (ko)
KR (1) KR910009077B1 (ko)

Cited By (1)

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CN113611245A (zh) * 2021-08-17 2021-11-05 深圳市绿源半导体技术有限公司 一种双向传输装置及控制方法

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GB2226727B (en) * 1988-10-15 1993-09-08 Sony Corp Address decoder circuits for non-volatile memories
US5095465A (en) * 1990-01-05 1992-03-10 Board Of Regents The University Of Texas System In situ testing with surface seismic waves of materials having properties that change with time
DE69118214T2 (de) * 1990-01-23 1996-10-31 Nippon Electric Co Digitaler Halbleiterschaltkreis
GB9007791D0 (en) * 1990-04-06 1990-06-06 Foss Richard C High voltage boosted wordline supply charge pump and regulator for dram
GB9007790D0 (en) * 1990-04-06 1990-06-06 Lines Valerie L Dynamic memory wordline driver scheme
JPH04123388A (ja) * 1990-09-13 1992-04-23 Nec Corp 半導体メモリ装置
US5223751A (en) * 1991-10-29 1993-06-29 Vlsi Technology, Inc. Logic level shifter for 3 volt cmos to 5 volt cmos or ttl
US5276366A (en) * 1992-10-02 1994-01-04 Motorola, Inc. Digital voltage level translator circuit
JP3194636B2 (ja) * 1993-01-12 2001-07-30 三菱電機株式会社 レベル変換回路、レベル変換回路を内蔵したエミュレータ用マイクロコンピュータ、レベル変換回路を内蔵したピギーバックマイクロコンピュータ、レベル変換回路を内蔵したエミュレートシステム及びレベル変換回路を内蔵したｌｓｉテストシステム
JP3267436B2 (ja) * 1993-04-19 2002-03-18 三菱電機株式会社 半導体装置
US5397941A (en) * 1993-08-20 1995-03-14 National Semiconductor Corporation Interface circuits between powered down devices and a bus
US5796673A (en) 1994-10-06 1998-08-18 Mosaid Technologies Incorporated Delay locked loop implementation in a synchronous dynamic random access memory
JP3213179B2 (ja) * 1994-10-21 2001-10-02 東芝マイクロエレクトロニクス株式会社 半導体集積回路
US5644265A (en) * 1995-05-01 1997-07-01 International Business Machines Corporation Off-chip driver for mixed voltage applications
JP3152867B2 (ja) * 1995-08-25 2001-04-03 株式会社東芝 レベルシフト半導体装置
US5684415A (en) * 1995-12-22 1997-11-04 Symbios Logic Inc. 5 volt driver in a 3 volt CMOS process
US6118302A (en) * 1996-05-28 2000-09-12 Altera Corporation Interface for low-voltage semiconductor devices
US5819099A (en) * 1996-10-18 1998-10-06 Texas Instruments Incorporated Voltage converting I/O driver circuit
JP3705880B2 (ja) * 1996-11-28 2005-10-12 富士通株式会社 レベルコンバータ及び半導体装置
JP2002353805A (ja) * 2001-05-30 2002-12-06 Fujitsu Ltd 半導体回路
US20040061524A1 (en) * 2002-06-13 2004-04-01 Stmicroelectronics Pvt. Ltd. Digital electronic circuit for translating high voltage levels to low voltage levels
US20040032284A1 (en) * 2002-06-13 2004-02-19 Stmicroelectronics Pvt. Ltd. Digital electronic circuit for translating high voltage levels to low voltage levels
US6859084B2 (en) * 2002-08-19 2005-02-22 Elixent Ltd. Low-power voltage modulation circuit for pass devices
US6946903B2 (en) * 2003-07-28 2005-09-20 Elixent Limited Methods and systems for reducing leakage current in semiconductor circuits
KR100711108B1 (ko) * 2004-07-16 2007-04-24 삼성전자주식회사 레벨 쉬프터 및 레벨 쉬프팅 방법
US7385423B1 (en) * 2005-04-26 2008-06-10 Altera Corporation Low-power low-voltage buffer with half-latch
US7212060B1 (en) 2005-08-23 2007-05-01 Xilinx, Inc. Ground bounce protection circuit for a test mode pin
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113611245A (zh) * 2021-08-17 2021-11-05 深圳市绿源半导体技术有限公司 一种双向传输装置及控制方法
CN113611245B (zh) * 2021-08-17 2022-08-26 深圳市绿源半导体技术有限公司 一种双向传输装置及控制方法

Also Published As

Publication number Publication date
KR910009077B1 (ko) 1991-10-28
JPH01213022A (ja) 1989-08-25
US4926070A (en) 1990-05-15
JP2585348B2 (ja) 1997-02-26

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