KR900001131A - 반도체 집적회로의 출력회로 - Google Patents
반도체 집적회로의 출력회로 Download PDFInfo
- Publication number
- KR900001131A KR900001131A KR1019890007412A KR890007412A KR900001131A KR 900001131 A KR900001131 A KR 900001131A KR 1019890007412 A KR1019890007412 A KR 1019890007412A KR 890007412 A KR890007412 A KR 890007412A KR 900001131 A KR900001131 A KR 900001131A
- Authority
- KR
- South Korea
- Prior art keywords
- conductive
- mos transistor
- conductive type
- mos
- transistors
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09425—Multistate logic
- H03K19/09429—Multistate logic one of the states being the high impedance or floating state
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
- Dram (AREA)
Abstract
Description
Claims (2)
- 제1전원(VDD)전원과 제2전원(집지전위)사이에 직렬로 접속된 출력버퍼용 제1도전형 제1MOS트랜지스터(P1) 및 제2도전형 제1MOS트랜지스터(N1)와, 상기 2개의 MOS트랜지스터(P1,N1)사이에 접속되면서 상호 병렬로 접속된 제1도전형 제2MOS트랜지스터(P2)와 제2도전형 제2MOS트랜지스터(N2) 및, 상기 제1전원과 상기 제1도전형 제1MOS트랜지서터(P1)의 사이에 접속된 1개의 제1도전형 제3MOS트랜지스터(P3) 또는 복수의 제1도전형 제3트랜지스터로 이루어져 신호입력용으로 사용되는 제1논리소자부(61)와 ; 상기 제2도전형 제1MOS트랜지스터(N1)와 상기 제2전원사이에 접속된 1개의 제2도전형 제3MOS트랜지스터(N3) 또는 복수의 제2도전형 제3MOS트랜지스터로 이루어져 신호입력용으로 사용되는 제2논리소자부(62)를 구비하고 ; 상기 제1도전형 및 제2도전형 제2NOS트랜지스터(P2, N3)의 챈널폭보다도 작게 설정된 것을 특징으로 하는 반도체 집적회로의 출력회로.
- 제1항에 있어서, 상기 제1전원과 상기 제1도전형 제1MOS트랜지스터(P1)사이에 제1도전형 제4MOS트랜지스터(P4)가 접속되며, 상기 제1도전형 제1MOS트랜지스터(P1)와 상기 제2전원사이에 제2도전형의 제4MOS트랜지스터(P4)가 접속되며, 상기 제1도전형의 제4MOS트랜지스터(N4)와 상기 제2도전형 제2MOS트랜지스터(N2)의 각 게이트에 출력제어신호(EN)가 공급되고, 상기 제2도전형의 제4MOS트랜지스터(N4)와 상기 제1도전형의 제2MOS트랜지스터(P2)의 각 게이트에 상기 출력제어신호(EN)와는 상보적인 출력제어신호가 공급되며, 상기 제1도전형 및 제2도전형의 제2MOS트랜지스터(P2, N2)의 챈널폭이 상기 제1 및 제2도전형의 제3MOS트랜지스터(P3, N3)의 챈널폭보다도 작으면서 상기 제1 및 제2도전형의 제4MOS트랜지스터(P4, N4)의 챈널폭보다도 작게 설정된 것을 특징으로 하는 반도체 집적회로의출력회로.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP88-136366 | 1988-06-02 | ||
JP63136366A JPH01305616A (ja) | 1988-06-02 | 1988-06-02 | 半導体集積回路の出力回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900001131A true KR900001131A (ko) | 1990-01-31 |
KR920004341B1 KR920004341B1 (ko) | 1992-06-01 |
Family
ID=15173487
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890007412A KR920004341B1 (ko) | 1988-06-02 | 1989-05-31 | 반도체집적회로의 출력회로 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5034629A (ko) |
EP (1) | EP0344604A3 (ko) |
JP (1) | JPH01305616A (ko) |
KR (1) | KR920004341B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100449364B1 (ko) * | 1997-08-07 | 2004-12-04 | 삼성전자주식회사 | 인터럽트처리장치 |
Families Citing this family (38)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH07105711B2 (ja) * | 1990-04-26 | 1995-11-13 | 株式会社東芝 | 入力回路 |
EP0464239B1 (de) * | 1990-07-03 | 1996-11-27 | Siemens Aktiengesellschaft | Querstromfreie C-MOS-Verstärkerschaltung |
US5247212A (en) * | 1991-01-31 | 1993-09-21 | Thunderbird Technologies, Inc. | Complementary logic input parallel (clip) logic circuit family |
JP3014164B2 (ja) * | 1991-05-15 | 2000-02-28 | 沖電気工業株式会社 | 出力バッファ回路 |
US5120992A (en) * | 1991-07-03 | 1992-06-09 | National Semiconductor Corporation | CMOS output driver with transition time control circuit |
JP2824706B2 (ja) * | 1991-09-27 | 1998-11-18 | 三菱電機株式会社 | 電流源回路およびその動作方法 |
JP2670651B2 (ja) * | 1991-10-14 | 1997-10-29 | 三菱電機株式会社 | 出力装置 |
US5204557A (en) * | 1991-10-15 | 1993-04-20 | National Semiconductor Corporation | Digital signal level translator |
JP2959269B2 (ja) * | 1992-04-14 | 1999-10-06 | 三菱電機株式会社 | オープンドレイン出力回路 |
US5583457A (en) | 1992-04-14 | 1996-12-10 | Hitachi, Ltd. | Semiconductor integrated circuit device having power reduction mechanism |
US5418473A (en) * | 1992-10-28 | 1995-05-23 | Idaho Research Foundation, Inc. | Single event upset immune logic family |
US5367206A (en) * | 1993-06-17 | 1994-11-22 | Advanced Micro Devices, Inc. | Output buffer circuit for a low voltage EPROM |
US5428311A (en) * | 1993-06-30 | 1995-06-27 | Sgs-Thomson Microelectronics, Inc. | Fuse circuitry to control the propagation delay of an IC |
JP3162561B2 (ja) * | 1993-12-24 | 2001-05-08 | 株式会社東芝 | Cmos論理回路 |
JP3202481B2 (ja) * | 1994-05-30 | 2001-08-27 | 株式会社東芝 | 半導体集積回路 |
US5491429A (en) * | 1994-09-16 | 1996-02-13 | At&T Global Information Solutions Company | Apparatus for reducing current consumption in a CMOS inverter circuit |
US5701090A (en) | 1994-11-15 | 1997-12-23 | Mitsubishi Denki Kabushiki Kaisha | Data output circuit with reduced output noise |
JP3640703B2 (ja) * | 1995-05-24 | 2005-04-20 | 株式会社ルネサステクノロジ | バス駆動回路、レシーバ回路およびバスシステム |
TW487582B (en) * | 1995-08-11 | 2002-05-21 | Nissan Chemical Ind Ltd | Method for converting sparingly water-soluble medical substance to amorphous state |
US5880606A (en) * | 1995-12-01 | 1999-03-09 | Lucent Technologies Inc. | Programmable driver circuit for multi-source buses |
US5592104A (en) * | 1995-12-13 | 1997-01-07 | Lsi Logic Corporation | Output buffer having transmission gate and isolated supply terminals |
US5751180A (en) * | 1996-09-03 | 1998-05-12 | Motorola, Inc. | Electrical device structure having reduced crowbar current and power consumption |
US5781032A (en) * | 1996-09-09 | 1998-07-14 | International Business Machines Corporation | Programmable inverter circuit used in a programmable logic cell |
KR100219559B1 (ko) * | 1996-10-09 | 1999-09-01 | 윤종용 | 신호라인 구동회로 및 이를 구비하는 반도체장치 |
KR100273206B1 (ko) * | 1997-01-11 | 2000-12-15 | 김영환 | 문턱전압 변화에 둔감한 레벨쉬프터 |
US6008665A (en) * | 1997-05-07 | 1999-12-28 | California Micro Devices Corporation | Termination circuits and methods therefor |
US6278295B1 (en) | 1998-02-10 | 2001-08-21 | Cypress Semiconductor Corp. | Buffer with stable trip point |
US6445224B1 (en) * | 2001-01-16 | 2002-09-03 | Ubicom, Inc. | Reduced short current circuit |
DE10136320B4 (de) | 2001-07-26 | 2008-05-15 | Infineon Technologies Ag | Anordnung und Verfahren zum Umschalten von Transistoren |
US20070063738A1 (en) * | 2005-09-16 | 2007-03-22 | Fischer Timothy C | CMOS logic circuitry |
KR20070107963A (ko) * | 2006-05-04 | 2007-11-08 | 페어차일드코리아반도체 주식회사 | 고전압 게이트 드라이버용 로직회로 |
US7741879B2 (en) * | 2007-02-22 | 2010-06-22 | Avago Technologies Enterprise IP (Singapore) Pte. Ltd. | Apparatus and method for generating a constant logical value in an integrated circuit |
JP4475340B2 (ja) * | 2008-03-21 | 2010-06-09 | セイコーエプソン株式会社 | 温度補償回路 |
US20090243705A1 (en) * | 2008-03-28 | 2009-10-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | High Voltage Tolerative Driver Circuit |
US8773192B2 (en) | 2012-11-28 | 2014-07-08 | Lsi Corporation | Overshoot suppression for input/output buffers |
US9230671B2 (en) * | 2013-07-05 | 2016-01-05 | Kabushiki Kaisha Toshiba | Output circuit and semiconductor storage device |
JP6537892B2 (ja) * | 2014-05-30 | 2019-07-03 | 株式会社半導体エネルギー研究所 | 半導体装置、及び電子機器 |
US10790808B2 (en) * | 2017-01-24 | 2020-09-29 | Telefonaktiebolaget Lm Ericsson (Publ) | Variable delay circuits |
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US4295062A (en) * | 1979-04-02 | 1981-10-13 | National Semiconductor Corporation | CMOS Schmitt trigger and oscillator |
JPS55141828A (en) * | 1979-04-23 | 1980-11-06 | Hitachi Ltd | Complementary type mis circuit |
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US4507649A (en) * | 1982-05-24 | 1985-03-26 | Rca Corporation | Flash A/D converter having reduced input loading |
JPS5923915A (ja) * | 1982-07-30 | 1984-02-07 | Toshiba Corp | シユミツトトリガ回路 |
JPS61109320A (ja) * | 1984-11-02 | 1986-05-27 | Nec Corp | 出力バツフア回路 |
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KR920006438B1 (ko) * | 1985-04-22 | 1992-08-06 | 엘 에스 아이 로직 코포레이션 | 슬루 레이트(slew rate)가 제어되는 고속 CMOS 버퍼 |
JPS62284524A (ja) * | 1986-06-02 | 1987-12-10 | Mitsubishi Electric Corp | 相補型mos集積回路 |
DE3784285T2 (de) * | 1986-08-29 | 1993-07-22 | Mitsubishi Electric Corp | Integrierte komplementaere mos-schaltung. |
JPS6360625A (ja) * | 1986-08-29 | 1988-03-16 | Mitsubishi Electric Corp | 3ステ−ト付相補型mos集積回路 |
JPS6388918A (ja) * | 1986-10-01 | 1988-04-20 | Mitsubishi Electric Corp | 相補型mos集積回路 |
US4725747A (en) * | 1986-08-29 | 1988-02-16 | Texas Instruments Incorporated | Integrated circuit distributed geometry to reduce switching noise |
-
1988
- 1988-06-02 JP JP63136366A patent/JPH01305616A/ja active Pending
-
1989
- 1989-05-24 EP EP89109394A patent/EP0344604A3/en not_active Withdrawn
- 1989-05-31 KR KR1019890007412A patent/KR920004341B1/ko not_active IP Right Cessation
-
1990
- 1990-07-16 US US07/552,855 patent/US5034629A/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100449364B1 (ko) * | 1997-08-07 | 2004-12-04 | 삼성전자주식회사 | 인터럽트처리장치 |
Also Published As
Publication number | Publication date |
---|---|
KR920004341B1 (ko) | 1992-06-01 |
EP0344604A3 (en) | 1990-04-25 |
US5034629A (en) | 1991-07-23 |
JPH01305616A (ja) | 1989-12-08 |
EP0344604A2 (en) | 1989-12-06 |
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