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KR890004238A - 순차접근 기억장치 - Google Patents

순차접근 기억장치 Download PDF

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Publication number
KR890004238A
KR890004238A KR1019880011230A KR880011230A KR890004238A KR 890004238 A KR890004238 A KR 890004238A KR 1019880011230 A KR1019880011230 A KR 1019880011230A KR 880011230 A KR880011230 A KR 880011230A KR 890004238 A KR890004238 A KR 890004238A
Authority
KR
South Korea
Prior art keywords
address
access memory
sequential access
word
memory
Prior art date
Application number
KR1019880011230A
Other languages
English (en)
Other versions
KR910009296B1 (ko
Inventor
고이찌 다쯔끼
Original Assignee
쓰지 하루오
샤프가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 쓰지 하루오, 샤프가부시끼가이샤 filed Critical 쓰지 하루오
Publication of KR890004238A publication Critical patent/KR890004238A/ko
Application granted granted Critical
Publication of KR910009296B1 publication Critical patent/KR910009296B1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Communication Control (AREA)
  • Memory System (AREA)

Abstract

내용 없음

Description

순차접근 기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 순차접근 기억장치의 일 실시예에서 회로구조를 표시하는 블록도. 제 2 도는 실시예에서 모듀로(modulo)(m ×2 + 1 ×2)카운터의 계산방법 표시도. 제 3 도는 실시예에서 M=3, 1=2의 결우에 카운터의 구체적인 회로 표시도.

Claims (1)

  1. (m ×2 + 1) 단어의 자료를 기억할 수 있는 기억수단과 단순한 계산작동을 반복하도록 (m+1) 어드레스에서 순차직으로 (m+1)에 어드레스들을 일으킨후 또다시 No.1의 어드레스를 일으키고 기억수단의 No.1에서 순차적으로 (m ×2 + 1) 어드레스에 어드레스들을 일으킨후 (m+1) 어드레스에 되돌아가도록 적응되고(m ×2 + 1 × 2) 기수의 자료를 기억할 수 있는 카운터, 소정의 지연시간에 그들을 출력하기 위해 카운터의 제어하에 1단어로 구성된 b부분과 그리고 m단어로 구성된 a부분의 두 시스템 자료를 입력하도록 기억수단의 어드레스를 일으키게한 것으로 이루어진 것을 특징으로 하는 순차접근 기억장치.
    ※ 참고사항 : 최초출원내용에 의하여 공개하는 것임.
KR1019880011230A 1987-08-31 1988-08-31 순차접근 기억장치 KR910009296B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62-218972 1987-08-31
JP62218972A JPS6461835A (en) 1987-08-31 1987-08-31 Sequential access memory

Publications (2)

Publication Number Publication Date
KR890004238A true KR890004238A (ko) 1989-04-20
KR910009296B1 KR910009296B1 (ko) 1991-11-09

Family

ID=16728245

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880011230A KR910009296B1 (ko) 1987-08-31 1988-08-31 순차접근 기억장치

Country Status (4)

Country Link
US (1) US4935902A (ko)
JP (1) JPS6461835A (ko)
KR (1) KR910009296B1 (ko)
CA (1) CA1315010C (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2765719B1 (fr) * 1997-07-04 1999-10-01 Sgs Thomson Microelectronics Perfectionnement aux memoires a acces sequentiels
JPH11126473A (ja) * 1997-10-24 1999-05-11 Fujitsu Ltd 半導体集積回路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4153951A (en) * 1976-09-24 1979-05-08 Itek Corporation Event marker having extremely small bit storage requirements
JPS5538603A (en) * 1978-09-04 1980-03-18 Nippon Telegr & Teleph Corp <Ntt> Semiconductor memory device

Also Published As

Publication number Publication date
US4935902A (en) 1990-06-19
KR910009296B1 (ko) 1991-11-09
JPH056214B2 (ko) 1993-01-26
JPS6461835A (en) 1989-03-08
CA1315010C (en) 1993-03-23

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