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KR880008337A - 반도체 기억장치 - Google Patents

반도체 기억장치 Download PDF

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Publication number
KR880008337A
KR880008337A KR870014302A KR870014302A KR880008337A KR 880008337 A KR880008337 A KR 880008337A KR 870014302 A KR870014302 A KR 870014302A KR 870014302 A KR870014302 A KR 870014302A KR 880008337 A KR880008337 A KR 880008337A
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KR
South Korea
Prior art keywords
semiconductor memory
memory device
bit lines
memory cell
partial bit
Prior art date
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Application number
KR870014302A
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English (en)
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KR910006112B1 (ko
Inventor
도오루 후루야마
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication of KR880008337A publication Critical patent/KR880008337A/ko
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/565—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using capacitive charge storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)

Abstract

내용 없음.

Description

반도체 기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 관한 반도체 기억장치의 구성를 도시해 놓은 회로도,
제2도, 제3도는 상기 실시예회로의 각부를 구체적으로 도시해 놓은 회로도.

Claims (13)

  1. 복수개의 메모리셀(12)과, 이 메모리셀(12)에 접속되는 비드선(BL1)을 구비하여서 된 반도체 기억장치에 있어서, 상기 비트선(BLI)에 형성되는 복수개의 부분 비트선(BL1a∼BL1c)과, 이 부분비트선(BL1a∼BL1c)을 접속 및 절단시켜 주는 스위칭 수단(11), 기준전위를 기억시겨 주는 기준전위 구단(13) 및, 기준전위와 더불어 어드레스된 메모리셀(12)의 줄력을 비교해 주는 감지증폭기 수단(SA1∼SA3)을 구비해서 n개 다른 기억전위를 사용한 n개 값의 데이터로 기억시켜 줄 수 있도록 된 반도체 기억장치.
  2. 제1항에 있어서, n값이 2m이고, 각 메모리셀(12)이 각각 m비트의 정보를 기억시켜 주는 것을 특징으로 하는 반도체 기억장치.
  3. 제1항에 있어서, 각 메모리셀이 정보기억용 캐패시터(31)와 선택용 트랜지스터(32)로 구성된 것을 특징으로 하는 반도체 기억장치.
  4. 제1항에 있어서, 스위칭 수단(11)이 부분비트선(BL1a∼BL1c)을 상호 연결해 주도록 각각 스위칭 소자로 이루어진 것을 특징으로 하는 반도체기억장치.
  5. 제1항에 있어서, 기준전위 수단(13)이 복수개의 모의 메모리셀로 이루어진 것을 특징으로 하는 반도체기억장치.
  6. 제5항에 있어서, 각 모의 메모리셀이 정보기억용 캐패시터(31)와 선택용 트랜지스터(32)로 이루어진 것을 특징으로 하는 반도체 기억장치.
  7. 제1항에 있어서, 감지증폭기 수단(SA1∼SA3)의 출력이 공급되는 데이터 검출 수단(41∼50)이 설치되고, 메모리셀(12)로부터 데이터를 독출한 때(n-1)개의 각 부분비트선전위중 l개가 각각의 기준전위보다도 더 높은 레벨인 것과, 상기 감지증폭기 수단(SA1-SA3)으로 판정될 때 데이터 거물 수단(41∼50)이 이를 n개 값의 정보 중(l+1)번째의 정보레벨로서 출력해 주는 것을 특징으로 하는 반도체 기억장치.
  8. 제1항에 있어서, 메모리셀(12)에 대해 데이터의 기록을 행하는 데이터 기록수단(61∼67)이 설치되고 이 데이터 기록수단(61∼68)은(n-1)개의 각 부분비트선전위중 l를 높은 레벨로, 나머지 전부를 낮은 레벨로 설정한 후(n-1)개의 각 부분비트선을 단락시켜 줌에 의해 데이터 기록이 행해지는 것을 특징으로 하는 반도체 기억장치.
  9. 제4항에 있어서,(n-1)개의 부분비트선을 접속해 주는 스위칭 소자(11)가 도통시 그 게이트에 각 부분지트선(BL1a∼BL1c) 전위의 높은 레벨보다 더 높은 전위가 인가되는 N챈널 MOS트랜지스터로 구성되고 있는 것을 특징으로 하는 반도체 기억장치.
  10. 제4항에 있어서, (n-1)개의 부분비트선을 접속해 주는 스위칭 소자(11)가 도통시 고 게이트에 각 부분비트선(BL1a∼BL1c) 전위의 낮은 레벨보다 더 낮은 전위가 인가되는 P채널 MOS트랜지스터로 구성되고 있는 것을 특징으로 하는 반도체 기억장치.
  11. 제4항에 있어서,(n-1)개의 부분비트선을 점슥해 주는 스위칭 소자(11)가 CMOS전달게이트로 구성된 것을 특징으로 하는 반도체 기억장치.
  12. 제6항에 있어서, 모의 메모리셀(13)의 캐패시터(31) 값이 메모리셀(120의 캐패시터(31) 값의정도로 설정되어 있는 것을 특징으로 하는 반도체 기억장치.
  13. 제5항에 있어서, 모의 메머리셀(13)은 메모리셀(12)의 최고 기억전위인 거의배(단,) 정도의 전위를 발생해 주는 것을 특징으로 하는 반도체 기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870014302A 1986-12-15 1987-12-15 다수값 정보기억방식의 반도체기억장치 Expired KR910006112B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP298398 1986-12-15
JP61298398A JPS63149900A (ja) 1986-12-15 1986-12-15 半導体メモリ
JP61-298398 1986-12-15

Publications (2)

Publication Number Publication Date
KR880008337A true KR880008337A (ko) 1988-08-30
KR910006112B1 KR910006112B1 (ko) 1991-08-13

Family

ID=17859185

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870014302A Expired KR910006112B1 (ko) 1986-12-15 1987-12-15 다수값 정보기억방식의 반도체기억장치

Country Status (5)

Country Link
US (1) US4841483A (ko)
EP (1) EP0273639B1 (ko)
JP (1) JPS63149900A (ko)
KR (1) KR910006112B1 (ko)
DE (1) DE3787163T2 (ko)

Cited By (1)

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Publication number Priority date Publication date Assignee Title
US11984147B2 (en) 2019-04-26 2024-05-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including sense amplifier and operation method of semiconductor device

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JPH02260298A (ja) * 1989-03-31 1990-10-23 Oki Electric Ind Co Ltd 不揮発性多値メモリ装置
JPH0834257B2 (ja) * 1990-04-20 1996-03-29 株式会社東芝 半導体メモリセル
JPH07122989B2 (ja) * 1990-06-27 1995-12-25 株式会社東芝 半導体記憶装置
JP2528737B2 (ja) * 1990-11-01 1996-08-28 三菱電機株式会社 半導体記憶装置およびその製造方法
JP2573416B2 (ja) * 1990-11-28 1997-01-22 株式会社東芝 半導体記憶装置
US5218569A (en) * 1991-02-08 1993-06-08 Banks Gerald J Electrically alterable non-volatile memory with n-bits per memory cell
JP2564046B2 (ja) * 1991-02-13 1996-12-18 株式会社東芝 半導体記憶装置
EP0503633B1 (en) * 1991-03-14 1997-10-22 Kabushiki Kaisha Toshiba Semiconductor memory device
JP3181311B2 (ja) * 1991-05-29 2001-07-03 株式会社東芝 半導体記憶装置
JP3464803B2 (ja) * 1991-11-27 2003-11-10 株式会社東芝 半導体メモリセル
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JPH08180688A (ja) * 1994-12-26 1996-07-12 Nec Corp 半導体記憶装置
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11984147B2 (en) 2019-04-26 2024-05-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including sense amplifier and operation method of semiconductor device

Also Published As

Publication number Publication date
KR910006112B1 (ko) 1991-08-13
JPS63149900A (ja) 1988-06-22
US4841483A (en) 1989-06-20
DE3787163D1 (de) 1993-09-30
EP0273639B1 (en) 1993-08-25
DE3787163T2 (de) 1994-02-17
EP0273639A3 (en) 1990-05-16
EP0273639A2 (en) 1988-07-06
JPH059878B2 (ko) 1993-02-08

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Not in force date: 20040814

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

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St.27 status event code: N-4-6-H10-H13-oth-PC1903

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