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KR880005760A - Pll 회로용 위상 변별기 - Google Patents

Pll 회로용 위상 변별기 Download PDF

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Publication number
KR880005760A
KR880005760A KR870011278A KR870011278A KR880005760A KR 880005760 A KR880005760 A KR 880005760A KR 870011278 A KR870011278 A KR 870011278A KR 870011278 A KR870011278 A KR 870011278A KR 880005760 A KR880005760 A KR 880005760A
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KR
South Korea
Prior art keywords
pulse
pll circuit
phase discriminator
string
input
Prior art date
Application number
KR870011278A
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English (en)
Other versions
KR960012798B1 (ko
Inventor
숄쯔 베르너
Original Assignee
로베르트 아인젤
도이체 톰손-브란트 게엡베하
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 로베르트 아인젤, 도이체 톰손-브란트 게엡베하 filed Critical 로베르트 아인젤
Publication of KR880005760A publication Critical patent/KR880005760A/ko
Application granted granted Critical
Publication of KR960012798B1 publication Critical patent/KR960012798B1/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Measuring Phase Differences (AREA)
  • Manipulation Of Pulses (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

내용 없음

Description

PLL 회로용 위상 변별기
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 c는 본 발명에 따라 형성된 위상변별기의 특성곡선.
제4도는 본 발명을 실시하기 위한 회로도.
제5도는 제4의 작동방식을 설명하기 위한 곡선.

Claims (7)

  1. PLL 회로에서 제 1 및 제 2 펄스열(B, C)사이와 위상차이(ø)에 의존한 출력전압(UR)을 발생시키기 위한 위상 변별기에 있어서, 특성곡선(제3도c)의 상승은 출력전압(UR)의 위상차이(ø)에 대한 의존도를 나타내며 위상밀도분포(제3동b)에 상응하는 것을 특징으로 하는 PLL 회로용 위상변별기.
  2. 제 1항에 있어서, 제1펄스열(B)이 비트열(A)의 레벨 변동의 시간적위치를 표시하는 펄스로 구성되고, 제2펄스열은 등간격의 레벨 변동을 갖는 비트크럭(C)이고, 진행방향에 따른 영향은 해당하는 펄스의 관련면 이 제 2 펄스열(C)의 양과 또는 음의 절반파로 떨어지는지의 여부에 의존하는 반면 제 1 펄스열(B)의 각각의 펄스는 출력전압(UR)에 크기에 따라라 동일한 방식으로 영향을 주는 것을 특징으로 하는 PLL 회로영 위상 변별기
  3. 제 2항에 있어서, 제 1 펄스열(B)은 클럭입력에 공급되며 제2펄스열(C)은 D형플립플롭(6)의 D입력에 공급되고, D형플립플롭(6)의 출력전압(Ω)은 2개의 출력(E,F)중 어느것에 제1펄스열(B)의 펄스가 전송되는지를 결정하며, 두개의 출력(E, F)에 있는 펄스는 반대극성을 갖고,·출력전압은 두개의 출력(E, F)에 있는 전압의 가신기(10)에 의해 형성되는 것을 특징으로 하는 PLL 회로용 위상변별기.
  4. 제2항 또는 3항에 있어서, 펄스가 주로 교란신호에 의해 발생될 확률이 생기자마자, 제1펄스열(B)의 펄스가 차단되는 것을 특징으로 하는 PLL회로용 위상변별기.
  5. 제 2항 내지 43항중 어느 한항 또는 다수항에 있어서 제1펄스열(B)의 펄스가 업/다운 카운터(16)에 의해 카운팅되는데, 이때 카운팅방향은 펄스가 제2펄스열(C)의 양 또는 음의 절반파로 떨어지는지의 여부에 의존하며, 카운팅 결과가 DA변환기 (17)에 의해 출력전압(UR)의 보충으로 이용되는 전압(U0)으로 변환되는 것을 특징으로 하는 PLL 회로 위상 변별기.
  6. 제 5항에 있어서, 업/다운카운터(I6)는 분리된 카운팅 입력을 갖고, 이러한 입력은 주파수분할기(18, 19)에 선접속되는 것을 특징으로 하는 PLL 회로용 위상변별기.
  7. 제 5 또는 6항에 있어서 업/다운카운터(16)외 카운팅 결과는 일시 기억이 아닌 기억장치내에 입력되는 것을 특징으로 하는 PLL 회로용 위상변별기.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870011278A 1986-10-11 1987-10-10 Pll 회로용 위상 변별기 KR960012798B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DEP3634751.5 1986-10-11
DE3634751.5 1986-10-11
DE19863634751 DE3634751A1 (de) 1986-10-11 1986-10-11 Phasendiskriminator, insbesondere fuer eine pll-schaltung

Publications (2)

Publication Number Publication Date
KR880005760A true KR880005760A (ko) 1988-06-30
KR960012798B1 KR960012798B1 (ko) 1996-09-24

Family

ID=6311581

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870011278A KR960012798B1 (ko) 1986-10-11 1987-10-10 Pll 회로용 위상 변별기

Country Status (7)

Country Link
EP (1) EP0264035B1 (ko)
JP (1) JP2941276B2 (ko)
KR (1) KR960012798B1 (ko)
AT (1) ATE90819T1 (ko)
DE (2) DE3634751A1 (ko)
ES (1) ES2041666T3 (ko)
HK (1) HK105495A (ko)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07101847B2 (ja) * 1988-10-21 1995-11-01 シャープ株式会社 デジタルフェイズロックドループ装置
US5410557A (en) * 1989-08-30 1995-04-25 Deutsche Thomson-Brandt Gmbh Method and apparatus for recognizing valid components in a digital signal
DE3928676A1 (de) * 1989-08-30 1991-03-07 Thomson Brandt Gmbh Schaltung zur erkennung eines nutzsignals in einem binaeren signal
DE4119452A1 (de) * 1991-06-13 1992-12-17 Thomson Brandt Gmbh Pll-schaltung mit einem zaehlphasendiskriminator
US5375148A (en) * 1993-03-01 1994-12-20 Motorola, Inc. VCO bias generator in a phase lock loop
DE19513080C1 (de) * 1995-04-07 1996-11-14 Bosch Gmbh Robert Demodulator für orthogonal modulierte Trägersignale
WO2006087782A1 (ja) * 2005-02-17 2006-08-24 Kyocera Kinseki Corporation 波形測定装置の評価装置および評価方法ならびにジッター測定方法
MD4067C1 (ro) * 2008-08-26 2011-03-31 Институт Электронной Инженерии И Промышленных Технологий Академии Наук Молдовы Procedeu de reglare a tensiunii cu convertizoare de impulsuri de ridicare şi inversare

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE324835B (ko) * 1968-10-14 1970-06-15 Asea Ab
US3701039A (en) * 1968-10-28 1972-10-24 Ibm Random binary data signal frequency and phase compensation circuit
US3646455A (en) * 1970-10-08 1972-02-29 Mohawk Data Sciences Corp Phase-detecting circuit
US3902128A (en) * 1974-08-05 1975-08-26 Motorola Inc Frequency/phase comparator
GB1547360A (en) * 1975-12-01 1979-06-13 Gen Electric Co Ltd Apparatus for indicating the sequence of alternating current signals
DE2809315B2 (de) * 1978-03-03 1980-01-03 Siemens Ag, 1000 Berlin Und 8000 Muenchen Digitaler Frequenzdiskriminator
JPS5551100U (ko) * 1978-10-02 1980-04-03
US4330759A (en) * 1980-03-05 1982-05-18 Bell Telephone Laboratories, Incorporated Apparatus for generating synchronized timing pulses from binary data signals
DE3138964A1 (de) * 1981-09-30 1983-04-14 Siemens AG, 1000 Berlin und 8000 München Verfahren zur unterdrueckung von stoerungen bei dem phasenvergleich zweier wechselspannungssignale, insbesondere bei dem phasenvergleich in ultraschall-echosignal-phasendetektoranordnungen fuer raumueberwachungsgeraete
JPS6047515A (ja) * 1983-08-26 1985-03-14 Victor Co Of Japan Ltd 同期引込判別回路
DE3520301A1 (de) * 1984-06-16 1985-12-19 ANT Nachrichtentechnik GmbH, 7150 Backnang Phasenvergleichsverfahren
JPS6130814A (ja) * 1984-07-10 1986-02-13 ジヨン・フリユ−ク・マニフアクチヤリング．カムパニ−，インコ−ポレ−テツド デジタル式位相検波器

Also Published As

Publication number Publication date
JP2941276B2 (ja) 1999-08-25
ES2041666T3 (es) 1993-12-01
ATE90819T1 (de) 1993-07-15
DE3634751A1 (de) 1988-04-14
EP0264035A3 (en) 1989-07-26
EP0264035B1 (de) 1993-06-16
KR960012798B1 (ko) 1996-09-24
HK105495A (en) 1995-07-07
DE3786221D1 (de) 1993-07-22
EP0264035A2 (de) 1988-04-20
JPS63114412A (ja) 1988-05-19

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