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ES2041666T3 - Discriminador de fase en particular para circuito pll. - Google Patents

Discriminador de fase en particular para circuito pll.

Info

Publication number
ES2041666T3
ES2041666T3 ES198787114407T ES87114407T ES2041666T3 ES 2041666 T3 ES2041666 T3 ES 2041666T3 ES 198787114407 T ES198787114407 T ES 198787114407T ES 87114407 T ES87114407 T ES 87114407T ES 2041666 T3 ES2041666 T3 ES 2041666T3
Authority
ES
Spain
Prior art keywords
pll circuit
phase discriminator
phase
dropouts
regeneration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES198787114407T
Other languages
English (en)
Inventor
Werner Dipl.-Ing. Scholz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Deutsche Thomson Brandt GmbH
Original Assignee
Deutsche Thomson Brandt GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche Thomson Brandt GmbH filed Critical Deutsche Thomson Brandt GmbH
Application granted granted Critical
Publication of ES2041666T3 publication Critical patent/ES2041666T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Measuring Phase Differences (AREA)
  • Manipulation Of Pulses (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

DISCRIMINADOR DE FASE PARA UNA CONEXION PLL DE GENERACION DE INTERVALO BIT Y CODIFICACION O REGENERACION DE UNA CADENCIA DE BIT (A) TRANSMITIDA.EL INVENTO CORRESPONDE A LA INCLINACION DE LA CURVA CARACTERISTICA (3C) DEL DISCRIMINADOR SEGUN LA DISTRIBUCION DE FASE (3B). SE IMPIDE QUE DESVIACIONES GRANDES DE FASES PRODUCIDAS EN INSTANTES BREVES DE TIEMPO INFLUYAN SOBRE LA TENSION DE REGULACION (UR)
ES198787114407T 1986-10-11 1987-10-02 Discriminador de fase en particular para circuito pll. Expired - Lifetime ES2041666T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19863634751 DE3634751A1 (de) 1986-10-11 1986-10-11 Phasendiskriminator, insbesondere fuer eine pll-schaltung

Publications (1)

Publication Number Publication Date
ES2041666T3 true ES2041666T3 (es) 1993-12-01

Family

ID=6311581

Family Applications (1)

Application Number Title Priority Date Filing Date
ES198787114407T Expired - Lifetime ES2041666T3 (es) 1986-10-11 1987-10-02 Discriminador de fase en particular para circuito pll.

Country Status (7)

Country Link
EP (1) EP0264035B1 (es)
JP (1) JP2941276B2 (es)
KR (1) KR960012798B1 (es)
AT (1) ATE90819T1 (es)
DE (2) DE3634751A1 (es)
ES (1) ES2041666T3 (es)
HK (1) HK105495A (es)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07101847B2 (ja) * 1988-10-21 1995-11-01 シャープ株式会社 デジタルフェイズロックドループ装置
DE3928676A1 (de) * 1989-08-30 1991-03-07 Thomson Brandt Gmbh Schaltung zur erkennung eines nutzsignals in einem binaeren signal
US5410557A (en) * 1989-08-30 1995-04-25 Deutsche Thomson-Brandt Gmbh Method and apparatus for recognizing valid components in a digital signal
DE4119452A1 (de) * 1991-06-13 1992-12-17 Thomson Brandt Gmbh Pll-schaltung mit einem zaehlphasendiskriminator
US5375148A (en) * 1993-03-01 1994-12-20 Motorola, Inc. VCO bias generator in a phase lock loop
DE19513080C1 (de) * 1995-04-07 1996-11-14 Bosch Gmbh Robert Demodulator für orthogonal modulierte Trägersignale
JP4763683B2 (ja) * 2005-02-17 2011-08-31 京セラキンセキ株式会社 波形測定装置の評価装置および評価方法ならびにジッター測定方法
MD4067C1 (ro) * 2008-08-26 2011-03-31 Институт Электронной Инженерии И Промышленных Технологий Академии Наук Молдовы Procedeu de reglare a tensiunii cu convertizoare de impulsuri de ridicare şi inversare

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE324835B (es) * 1968-10-14 1970-06-15 Asea Ab
US3701039A (en) * 1968-10-28 1972-10-24 Ibm Random binary data signal frequency and phase compensation circuit
US3646455A (en) * 1970-10-08 1972-02-29 Mohawk Data Sciences Corp Phase-detecting circuit
US3902128A (en) * 1974-08-05 1975-08-26 Motorola Inc Frequency/phase comparator
GB1547360A (en) * 1975-12-01 1979-06-13 Gen Electric Co Ltd Apparatus for indicating the sequence of alternating current signals
DE2809315B2 (de) * 1978-03-03 1980-01-03 Siemens Ag, 1000 Berlin Und 8000 Muenchen Digitaler Frequenzdiskriminator
JPS5551100U (es) * 1978-10-02 1980-04-03
US4330759A (en) * 1980-03-05 1982-05-18 Bell Telephone Laboratories, Incorporated Apparatus for generating synchronized timing pulses from binary data signals
DE3138964A1 (de) * 1981-09-30 1983-04-14 Siemens AG, 1000 Berlin und 8000 München Verfahren zur unterdrueckung von stoerungen bei dem phasenvergleich zweier wechselspannungssignale, insbesondere bei dem phasenvergleich in ultraschall-echosignal-phasendetektoranordnungen fuer raumueberwachungsgeraete
JPS6047515A (ja) * 1983-08-26 1985-03-14 Victor Co Of Japan Ltd 同期引込判別回路
DE3520301A1 (de) * 1984-06-16 1985-12-19 ANT Nachrichtentechnik GmbH, 7150 Backnang Phasenvergleichsverfahren
JPS6130814A (ja) * 1984-07-10 1986-02-13 ジヨン・フリユ−ク・マニフアクチヤリング．カムパニ−，インコ−ポレ−テツド デジタル式位相検波器

Also Published As

Publication number Publication date
DE3786221D1 (de) 1993-07-22
DE3634751A1 (de) 1988-04-14
HK105495A (en) 1995-07-07
KR880005760A (ko) 1988-06-30
JPS63114412A (ja) 1988-05-19
KR960012798B1 (ko) 1996-09-24
ATE90819T1 (de) 1993-07-15
JP2941276B2 (ja) 1999-08-25
EP0264035B1 (de) 1993-06-16
EP0264035A2 (de) 1988-04-20
EP0264035A3 (en) 1989-07-26

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