KR860005285A - 이진 감산기단 - Google Patents

이진 감산기단

Info

Publication number: KR860005285A
Authority: KR; South Korea
Prior art keywords: exclusive; gate; output; borrow; input
Prior art date: 1984-12-14
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Granted

Application number

KR1019850009387A

Other languages

English (en)

Other versions

KR940004325B1 (ko

Inventor

아머 죤

Original Assignee

알씨에이 라이센싱 코포레이션

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1984-12-14

Filing date

1985-12-13

Publication date

1986-07-21

1985-12-13 Application filed by 알씨에이 라이센싱 코포레이션 filed Critical 알씨에이 라이센싱 코포레이션

1986-07-21 Publication of KR860005285A publication Critical patent/KR860005285A/ko

1994-05-19 Application granted granted Critical

1994-05-19 Publication of KR940004325B1 publication Critical patent/KR940004325B1/ko

2005-12-13 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal

Landscapes

General Physics & Mathematics (AREA)
Engineering & Computer Science (AREA)
Physics & Mathematics (AREA)
Computational Mathematics (AREA)
Mathematical Analysis (AREA)
Pure & Applied Mathematics (AREA)
Theoretical Computer Science (AREA)
Computing Systems (AREA)
Mathematical Optimization (AREA)
General Engineering & Computer Science (AREA)
Logic Circuits (AREA)
Manipulation Of Pulses (AREA)
Networks Using Active Elements (AREA)
Processing Of Color Television Signals (AREA)
Details Of Television Scanning (AREA)
Testing Of Coins (AREA)
Transforming Light Signals Into Electric Signals (AREA)
Magnetic Record Carriers (AREA)
Holo Graphy (AREA)
Credit Cards Or The Like (AREA)
Switches That Are Operated By Magnetic Or Electric Fields (AREA)
Crystals, And After-Treatments Of Crystals (AREA)
Electronic Switches (AREA)

KR1019850009387A 1984-12-14 1985-12-13 이진 감산기단 Expired - Fee Related KR940004325B1 (ko)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
US06/682,014 US4685079A (en)	1984-12-14	1984-12-14	Ripple-borrow binary subtraction circuit
US682,014		1984-12-14

Publications (2)

Publication Number	Publication Date
KR860005285A true KR860005285A (ko)	1986-07-21
KR940004325B1 KR940004325B1 (ko)	1994-05-19

Family

ID=24737826

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
KR1019850009387A Expired - Fee Related KR940004325B1 (ko)	1984-12-14	1985-12-13	이진 감산기단

Country Status (10)

Country	Link
US (1)	US4685079A (ko)
EP (1)	EP0185504B1 (ko)
JP (1)	JPH0746312B2 (ko)
KR (1)	KR940004325B1 (ko)
AT (1)	ATE77888T1 (ko)
AU (1)	AU576408B2 (ko)
CA (1)	CA1252897A (ko)
DE (1)	DE3586283T2 (ko)
ES (1)	ES8705130A1 (ko)
HK (1)	HK88497A (ko)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4709346A (en) *	1985-04-01	1987-11-24	Raytheon Company	CMOS subtractor
JPS62103732A (ja) *	1985-10-30	1987-05-14	Mitsubishi Electric Corp	Ｍｏｓトランジスタ回路
GB8531380D0 (en) *	1985-12-20	1986-02-05	Texas Instruments Ltd	Multi-stage parallel binary adder
JPH087672B2 (ja) *	1986-04-04	1996-01-29	松下電器産業株式会社	減算セル
US4739503A (en) *	1986-04-21	1988-04-19	Rca Corporation	Carry/borrow propagate adder/subtractor
JPH0810427B2 (ja) *	1986-11-07	1996-01-31	松下電器産業株式会社	減算セル
FR2612660B1 (fr) *	1987-03-18	1990-10-19	Hmida Hedi	Dispositif de calcul binaire
IT1210751B (it) *	1987-05-20	1989-09-20	Cselt Centro Studi Lab Telecom	Sommatore veloce in tecnologia c mos
DE3880409T2 (de) *	1987-09-23	1993-11-25	France Telecom	Binäre Additions- und Multiplikationsvorrichtung.
JP2563467B2 (ja) *	1988-04-20	1996-12-11	富士通株式会社	２進演算器
US4935719A (en) *	1989-03-31	1990-06-19	Sgs-Thomson Microelectronics, Inc.	Comparator circuitry
US7073720B2 (en)	1994-06-22	2006-07-11	Scientific Gaines International, Inc.	Lottery ticket bar code
KR100255962B1 (ko) *	1995-11-03	2000-05-01	윤종용	3-상태회로의 출력 안정화회로
US6018757A (en) *	1996-08-08	2000-01-25	Samsung Electronics Company, Ltd.	Zero detect for binary difference
EP1271303A1 (en) *	2001-06-22	2003-01-02	STMicroelectronics S.r.l.	A binary number comparator
US8707225B1 (en) *	2006-04-07	2014-04-22	Cadence Design Systems, Inc.	Synthesis of area-efficient subtractor and divider functional blocks
US7991820B1 (en)	2007-08-07	2011-08-02	Leslie Imre Sohay	One step binary summarizer
JP2009301210A (ja) *	2008-06-11	2009-12-24	Tokyo Denki Univ	Ｎ桁減算器ユニット、ｎ桁減算器モジュール、ｎ桁加算器ユニット及びｎ桁加算器モジュール
RU2621375C1 (ru) *	2015-12-08	2017-06-02	Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Ульяновский государственный технический университет"	Двоичный вычитатель
KR20210153433A (ko)	2020-06-10	2021-12-17	에스케이하이닉스 주식회사	연산 회로

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US3767906A (en) *	1972-01-21	1973-10-23	Rca Corp	Multifunction full adder
US4052604A (en) *	1976-01-19	1977-10-04	Hewlett-Packard Company	Binary adder
US4152775A (en) *	1977-07-20	1979-05-01	Intel Corporation	Single line propagation adder and method for binary addition
JPS54127645A (en) *	1978-03-28	1979-10-03	Fujitsu Ltd	Full subtractor using josephson logic gate
US4357675A (en) *	1980-08-04	1982-11-02	Bell Telephone Laboratories, Incorporated	Ripple-carry generating circuit with carry regeneration
US4425623A (en) *	1981-07-14	1984-01-10	Rockwell International Corporation	Lookahead carry circuit apparatus
US4439835A (en) *	1981-07-14	1984-03-27	Rockwell International Corporation	Apparatus for and method of generation of ripple carry signals in conjunction with logical adding circuitry
US4471454A (en) *	1981-10-27	1984-09-11	Ibm Corporation	Fast, efficient, small adder
US4523292A (en) *	1982-09-30	1985-06-11	Rca Corporation	Complementary FET ripple carry binary adder circuit
JPS5999541A (ja) *	1982-11-29	1984-06-08	Nec Corp	算術論理演算回路
JPS59139447A (ja) *	1983-01-28	1984-08-10	Matsushita Electric Ind Co Ltd	全加算器

1984
- 1984-12-14 US US06/682,014 patent/US4685079A/en not_active Expired - Lifetime
1985
- 1985-12-04 CA CA000496874A patent/CA1252897A/en not_active Expired
- 1985-12-06 AU AU50865/85A patent/AU576408B2/en not_active Expired
- 1985-12-06 ES ES549655A patent/ES8705130A1/es not_active Expired
- 1985-12-10 EP EP85308965A patent/EP0185504B1/en not_active Expired - Lifetime
- 1985-12-10 AT AT85308965T patent/ATE77888T1/de not_active IP Right Cessation
- 1985-12-10 DE DE8585308965T patent/DE3586283T2/de not_active Expired - Lifetime
- 1985-12-13 JP JP60281851A patent/JPH0746312B2/ja not_active Expired - Fee Related
- 1985-12-13 KR KR1019850009387A patent/KR940004325B1/ko not_active Expired - Fee Related
1997
- 1997-06-26 HK HK88497A patent/HK88497A/en not_active IP Right Cessation

Also Published As

Publication number	Publication date
ES8705130A1 (es)	1987-04-16
CA1252897A (en)	1989-04-18
AU5086585A (en)	1986-06-19
JPS61143842A (ja)	1986-07-01
DE3586283D1 (de)	1992-08-06
EP0185504A3 (en)	1988-06-15
DE3586283T2 (de)	1992-12-10
HK88497A (en)	1997-06-27
AU576408B2 (en)	1988-08-25
ATE77888T1 (de)	1992-07-15
EP0185504A2 (en)	1986-06-25
JPH0746312B2 (ja)	1995-05-17
EP0185504B1 (en)	1992-07-01
ES549655A0 (es)	1987-04-16
KR940004325B1 (ko)	1994-05-19
US4685079A (en)	1987-08-04

Publication	Publication Date	Title
KR860005285A (ko)	1986-07-21	이진 감산기단
JPS6471217A (en)	1989-03-16	Output buffer circuit
KR890004212B1 (en)	1989-10-27	Complementary logic circuit
EP0369716A3 (en)	1991-01-16	Amplifying circuit
EP0685807A4 (en)	1997-08-13	INTEGRATED SEMICONDUCTOR CIRCUIT.
KR900003072B1 (en)	1990-05-07	Phase comparator
EP0187698A3 (en)	1989-06-28	Balanced full adder circuit
GB1370714A (en)	1974-10-16	Integrated bistable circuit
DE3584421D1 (de)	1991-11-21	Emittergekoppelte logische schaltungen.
GB2075781A (en)	1981-11-18	Sample and hold circuit with offset cancellation
JPS57132268A (en)	1982-08-16	Digital signal processing circuit
GB1290057A (ko)	1972-09-20
KR890004465B1 (en)	1989-11-04	Delay circuit for gate array
JPS55656A (en)	1980-01-07	Complementary mos logic circuit
JPS57197910A (en)	1982-12-04	Comparator circuit
SU1182665A1 (ru)	1985-09-30	Элемент с трем состо ни ми
KR890004467B1 (en)	1989-11-04	Semiconductor latch circuit with noise resistance circuit
JPS57157639A (en)	1982-09-29	Semiconductor circuit
SU1492452A1 (ru)	1989-07-07	Триггер со счетным входом на взаимодополн ющих МДП-транзисторах
JPS6441924A (en)	1989-02-14	Logic circuit
KR830008614A (ko)	1983-12-10	매트릭스(matrix) 회로
JPS57176516A (en)	1982-10-29	Pcm signal device
JPS52144253A (en)	1977-12-01	Flip-flop circuit
JPS56126316A (en)	1981-10-03	Mos comparing integrated circuit
JPS56105539A (en)	1981-08-22	Adder of pcm signal

Legal Events

Date	Code	Title	Description
1985-12-13	PA0109	Patent application	St.27 status event code: A-0-1-A10-A12-nap-PA0109
1985-12-13	R17-X000	Change to representative recorded	St.27 status event code: A-3-3-R10-R17-oth-X000
1986-07-21	PG1501	Laying open of application	St.27 status event code: A-1-1-Q10-Q12-nap-PG1501
1990-11-20	A201	Request for examination
1990-11-20	PA0201	Request for examination	St.27 status event code: A-1-2-D10-D11-exm-PA0201
1994-04-27	G160	Decision to publish patent application
1994-05-19	PG1605	Publication of application before grant of patent	St.27 status event code: A-2-2-Q10-Q13-nap-PG1605
1994-07-27	E701	Decision to grant or registration of patent right
1994-07-27	PE0701	Decision of registration	St.27 status event code: A-1-2-D10-D22-exm-PE0701
1994-08-09	GRNT	Written decision to grant
1994-08-09	PR0701	Registration of establishment	St.27 status event code: A-2-4-F10-F11-exm-PR0701
1994-08-09	PR1002	Payment of registration fee	St.27 status event code: A-2-2-U10-U11-oth-PR1002 Fee payment year number: 1
1997-04-23	PR1001	Payment of annual fee	St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 4
1998-05-08	PR1001	Payment of annual fee	St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 5
1999-03-27	PR1001	Payment of annual fee	St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 6
2000-04-19	PR1001	Payment of annual fee	St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 7
2001-04-19	PR1001	Payment of annual fee	St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 8
2002-04-23	PR1001	Payment of annual fee	St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 9
2003-04-18	PR1001	Payment of annual fee	St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 10
2004-04-29	FPAY	Annual fee payment	Payment date: 20040430 Year of fee payment: 11
2004-04-30	PR1001	Payment of annual fee	St.27 status event code: A-4-4-U10-U11-oth-PR1001 Fee payment year number: 11
2005-05-20	LAPS	Lapse due to unpaid annual fee
2005-05-20	PC1903	Unpaid annual fee	St.27 status event code: A-4-4-U10-U13-oth-PC1903 Not in force date: 20050520 Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE
2006-04-10	PC1903	Unpaid annual fee	St.27 status event code: N-4-6-H10-H13-oth-PC1903 Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE Not in force date: 20050520
2018-06-07	P22-X000	Classification modified	St.27 status event code: A-4-4-P10-P22-nap-X000