JPS57157639A - Semiconductor circuit - Google Patents
Semiconductor circuitInfo
- Publication number
- JPS57157639A JPS57157639A JP56042903A JP4290381A JPS57157639A JP S57157639 A JPS57157639 A JP S57157639A JP 56042903 A JP56042903 A JP 56042903A JP 4290381 A JP4290381 A JP 4290381A JP S57157639 A JPS57157639 A JP S57157639A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- fets
- reduced
- logical operation
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 230000003111 delayed effect Effects 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To shorten delayed times and to reduce the number of constituting elements, by constituting logical operation circuits of Y=-A.B and Y=-A+B with two transistors. CONSTITUTION:A logical operation circuit of Y=-A.B is composed of an inverter 1 and an AND circuit 2. An input terminal 3 at one end is connected to an output terminal 5 through a P channel MOSFET 4. The terminal 5 is grounded through an N channel MOSFET 6, and an input terminal at the other end is connected to each gate of FETs 6 and 4. Moreover, another logical operation circuit Y=-A+B is composed of an inverter 12 and an OR circuit 13. Therefore, the number of constituting elements can be reduced to two FETs and the number of FETs through which signals pass can also be reduced, and thus, delayed times can be reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56042903A JPS57157639A (en) | 1981-03-24 | 1981-03-24 | Semiconductor circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56042903A JPS57157639A (en) | 1981-03-24 | 1981-03-24 | Semiconductor circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57157639A true JPS57157639A (en) | 1982-09-29 |
Family
ID=12648984
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56042903A Pending JPS57157639A (en) | 1981-03-24 | 1981-03-24 | Semiconductor circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57157639A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6219827U (en) * | 1985-07-19 | 1987-02-05 | ||
JPS63240126A (en) * | 1987-03-27 | 1988-10-05 | Toshiba Corp | Bimos logic circuit |
JPH03217114A (en) * | 1990-01-23 | 1991-09-24 | Matsushita Electric Ind Co Ltd | Glitch preventing circuit |
-
1981
- 1981-03-24 JP JP56042903A patent/JPS57157639A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6219827U (en) * | 1985-07-19 | 1987-02-05 | ||
JPS63240126A (en) * | 1987-03-27 | 1988-10-05 | Toshiba Corp | Bimos logic circuit |
JPH03217114A (en) * | 1990-01-23 | 1991-09-24 | Matsushita Electric Ind Co Ltd | Glitch preventing circuit |
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