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KR850001611A - Semiconductor memory - Google Patents

Semiconductor memory Download PDF

Info

Publication number
KR850001611A
KR850001611A KR1019840003761A KR840003761A KR850001611A KR 850001611 A KR850001611 A KR 850001611A KR 1019840003761 A KR1019840003761 A KR 1019840003761A KR 840003761 A KR840003761 A KR 840003761A KR 850001611 A KR850001611 A KR 850001611A
Authority
KR
South Korea
Prior art keywords
semiconductor memory
signal line
load
memory according
redundancy
Prior art date
Application number
KR1019840003761A
Other languages
Korean (ko)
Inventor
미쯔오(외 5) 이소베
Original Assignee
사바 쇼오이찌
가부시끼가이샤 도오시바(외 1)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 사바 쇼오이찌, 가부시끼가이샤 도오시바(외 1) filed Critical 사바 쇼오이찌
Publication of KR850001611A publication Critical patent/KR850001611A/en
Priority to KR2019900003082U priority Critical patent/KR900010670Y1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
    • G11C29/832—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

내용 없음No content

Description

반도체 메모리Semiconductor memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래 반도체 메모리의 일부 회로도, 제2도~제7도는 본 발명의 실시예이다.1 is a partial circuit diagram of a conventional semiconductor memory, and FIGS. 2 to 7 are embodiments of the present invention.

Claims (4)

용장용인 불량상태 구제용의 기억소자가 포함되어 있는 반도체 메모리에 있어서, 신호선에 삽입되는 퓨우즈소사, 비선택전압레벨의 전원이나 접지와 신호선사이에 접속되고 전기 퓨우즈 소자를 절단하므로써 신호선을 비선택화 하는 경우에 신호선을 비선택전압레벨로 보전시키는 부하등을 구비한 것을 특징으로 하는 반도체 메모리.A semiconductor memory including a redundancy memory device for redundancy, comprising: a fuse source inserted into a signal line, a power source of an unselected voltage level, or connected between a ground and a signal line and disconnecting the signal line by cutting off the electric fuse element. A semiconductor memory comprising a load or the like for holding a signal line at a non-selection voltage level when being selected. 제1항에 있어서, 부하는 저항소자인 것을 특징으로 하는 반도체 메모리.The semiconductor memory according to claim 1, wherein the load is a resistance element. 제1항에 있어서, 부하는 MOS트랜지스터인 것을 특징으로 하는 반도체 메모리.The semiconductor memory according to claim 1, wherein the load is a MOS transistor. 제1항에 있어서, 부하는 신호선 및 복수의 장소에 접속되는 것을 특징으로 하는 반도체 메모리.The semiconductor memory according to claim 1, wherein the load is connected to a signal line and a plurality of places. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019840003761A 1983-07-15 1984-06-29 Semiconductor memory KR850001611A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019900003082U KR900010670Y1 (en) 1983-07-15 1990-03-14 Semiconductor memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP58-127770 1983-07-15
JP58127770A JPS6020397A (en) 1983-07-15 1983-07-15 Semiconductor memory

Publications (1)

Publication Number Publication Date
KR850001611A true KR850001611A (en) 1985-03-30

Family

ID=14968258

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840003761A KR850001611A (en) 1983-07-15 1984-06-29 Semiconductor memory

Country Status (2)

Country Link
JP (1) JPS6020397A (en)
KR (1) KR850001611A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0480915B1 (en) * 1985-08-20 1995-11-22 STMicroelectronics, Inc. Defective element disabling circuit having a laser-blown fuse
JPH01251397A (en) * 1988-03-30 1989-10-06 Toshiba Corp Semiconductor memory device
JPH03142797A (en) * 1989-10-27 1991-06-18 Nec Ic Microcomput Syst Ltd Redundant circuit for semiconductor memory
JP2617617B2 (en) * 1990-11-16 1997-06-04 九州日本電気株式会社 Semiconductor memory
US5465233A (en) * 1993-05-28 1995-11-07 Sgs-Thomson Microelectronics, Inc. Structure for deselecting broken select lines in memory arrays
US5987632A (en) * 1997-05-07 1999-11-16 Lsi Logic Corporation Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56153588A (en) * 1980-04-25 1981-11-27 Toshiba Corp Storage device
JPS57210500A (en) * 1981-06-19 1982-12-24 Mitsubishi Electric Corp Semiconductor storage device

Also Published As

Publication number Publication date
JPS6020397A (en) 1985-02-01

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19840629

PG1501 Laying open of application
E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 19890715

Patent event code: PE09021S01D

E601 Decision to refuse application
PE0601 Decision on rejection of patent

Patent event date: 19900214

Comment text: Decision to Refuse Application

Patent event code: PE06012S01D

Patent event date: 19890715

Comment text: Notification of reason for refusal

Patent event code: PE06011S01I

PC1205 Withdrawal of application forming a basis of a converted application
WICV Withdrawal of application forming a basis of a converted application