KR900010670Y1 - Semiconductor memory - Google Patents

Abstract

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Description

Semiconductor memory

1 is a partial circuit diagram of a conventional semiconductor memory.

2 to 7 are circuit diagrams according to embodiments of the present invention, respectively.

* Explanation of symbols for main parts of the drawings

1: selection circuit 2: memory cell

3: power supply terminal 4, 5: high resistance load

6, 7: N-channel transistors 8, 9: transfer gate

11: NAND circuit 1 2, 13: CMOS inverter

111: NOR circuits 211 to 213: transistors

FS: Fuse element WL, WL ₁ , WL ₂ : Word line

BL: Bit line SAD: Block address signal

RAD: Hang address signal T _N , T _P : Transistor

AD: address input

[Industrial use]

The present invention relates to a semiconductor memory having a redundancy memory cell for defective state relief.

[Traditional Technology and Problems]

FIG. 1 is a circuit diagram when a fuse element FS is provided on a word line in a semiconductor memory device. In the drawing, reference numeral AD denotes an address input and 1 denotes a selection circuit for selecting a word line. The NAND circuit 11 and the inverter 12 are comprised.

WL is a word line, BL is a bit line, 2 is a memory cell, 3 is a power supply terminal, 4 and 5 are high resistance loads, 6 and 7 are N-channel transistors, 8 and 9 are The transfer gate (N-channel transistor) is shown.

If a defective state is found in the memory cell, the laser cuts the fuse element FS connected to the word line WL to select the memory cell, so that, for example, even if the defective memory cell is selected, The signal is not transmitted so that the bad memory cell is not selected. At the same time, a signal corresponding to the selection signal of the defective memory cell is applied to the redundant control circuit so that one of the redundant memory cells (not shown) for remedy of defective state is selected so that the address signal is selected by the selection circuit (1). In this way, even if a bad memory cell is selected, it can be replaced with a redundant memory cell and selected.

However, in such a circuit, when the defective element occurs, the word line WL becomes floating when the fuse element FS is cut so that the word line WL is not selected. When the line WL is in a floating state, "non-selection" may be in a "selection" state due to noise caused by adjacent signal lines or the like in which the voltage level is likely to fluctuate, which causes a malfunction.

[Purpose of designation]

The present invention has been made in view of the above point, and an object thereof is to provide a semiconductor memory in which the word line WL is not made floating and thus erroneous selection can be prevented.

[Composition of design]

The present invention for achieving the above object is selected by the first word line WL ₁ directly connected to the memory cell 2, the selection circuit 1 to which an address signal is applied, and the selection circuit 1 being selected. The fuse FS is connected in series to the second word line WL ₂ , the first or second word lines WL ₁ , WL ₂ , and a redundancy defective merolicell for redundancy and is divided into a plurality of sections. In the semiconductor memory, an arbitrary section is formed from the plurality of sections while being provided between the first word line WL ₁ and the second word line WL _{2 while} the second word line WL ₂ is a first input. The fuse FS is connected between the gate circuit 111 having the selected partition address signal SAD as a second input, and between the first or second word lines WL ₁ and WL ₂ and a power supply terminal or a ground terminal. ), the cutting by the first or second word line (WL _1, WL ₂₎ In this case, the ratio has been selected first or second word line (WL _1, WL _2), a non-selection voltage Make up to a load _{(R, T P, T N} ) to maintain that bellows.

[Action]

According to the present invention configured as described above, the load between the word line and the power supply or the ground, such as a transistor or a transistor which is normally turned ON, is connected in a direction in which the cell is unselected. When this non-selection is made, the word lines do not become floating and the memory cells remain at the non-selected level so that they are not affected by noise or the like.

EXAMPLE

Hereinafter, each embodiment will be described in detail with reference to the accompanying drawings.

Here, the same reference numerals are attached to the corresponding places in FIG. 1, and detailed description thereof will be omitted.

FIG. 2 shows the first embodiment of the present invention. In the case of FIG. 2a, a high resistance R is provided between the word line WL and ground, and in FIG. The word line WL falls to the non-selection level when the transistor TN to be connected is connected to cut the fuse element FS.

FIG. 3 and FIG. 4 apply the word line to the present invention. When the direction in which the word lines follow is set to a row, and the direction in which the data lines follow is set to columns, the doubled word lines are formed. It is divided into several sections by the boundary line in the column direction, and the word lines connected to the memory cells 2 are selected by the partition address signal SAD for selecting such sections and the ordinary row address signal RAD. In this case, the signal line directly connected to the memory cell 2 with the Noah circuit 111 as the boundary is the first word line WL ₁ and the signal line selected by the normal row address RAD as the second word line. (WL ₂ ). Here, the first word line WL ₁ is unselected at the ground potential level, and the second word line WL ₂ is unselected at the positive power supply voltage level.

And FIG. 3 in the case where the second word line between (WL ₂₎ the fuse element bar, which is (FS) is inserted, the second word line (WL ₂₎ and the power supply (3) of positive first 3a degree is high In the case of FIG. 3B, the transistor T _P , which has a small conductance and is normally on, is connected in the case of FIG. 3B, and the second word line WL ₂ when the fuse FS is disconnected. ) Is maintained at a non-selection level (positive power supply potential).

FIG. 4, the first word line (WL ₁₎ fuse elements (FS) if the 4a degrees between the bar is inserted, the first word line (WL ₁₎ and ground, the high-resistance (R) is connected, the 4b in In the case of the figure, the transistor T _N , which has a small conductance and is normally turned on, is connected so that the first word line WL ₁ is maintained at an unselected level (ground potential) when the fuse element FS is cut. It is.

The above loads (resistance R, transistor T _N , T _P ) use high resistance that has little effect when selecting a normal operation in which the fuse element FS is not cut. When the fuse device FS is cut and deselected, a device having a value capable of dropping a word line to a non-selected level within a short time after inputting power is required.

5a, b, 6a, b, 7a, and b are examples of applications of circuits 2a, b, 3a, b, 4a, and b, respectively. In the case of non-selection, the N channel of the CMOS inverter 12 driving the word line (second word line WL _{2 in} FIG. 6 and the first word line WL _{1 in} FIG. 7) is shown in FIG. side, the P-channel side, of the CMOS inverter 13 in FIG. 3 in FIG. 4 by by removing the N-channel Noah circuit 111 cheukreul the load (R) (T _N) (T _P) connected to the word line In this case, the load does not need to be high resistance, since the load in this case must be directly at the non-selection level in the case of non-selection in the normal operation, but in the case of selection In the transistors 211 and 212 or the transistor 213 which drive the word lines rather than the time for which the load sustains the word lines to the unselected level, The duration of time must be shorter.

That is, in the circuit which does not connect the load to the conventional word line as shown in FIG. 1, when the fuse element FS is cut off when the redundant circuit is used, the word line becomes floating and the word line If it is left in a floating state, there is a possibility that the word line is charged with voltage due to noise caused by nearby signal lines, fluctuations in power supply, or the like, and the unselected word lines are difficult to operate.

To solve this problem, as shown in FIGS. 2 and 3 and 4, when the fuse element FS is cut by connecting a transistor having high resistance or conductance with a small on-state and a normally on state, a floating state is formed in the word line. By not generating it, it is possible to maintain the non-selection level.

In Figs. 5 to 7, since non-high resistance is used as the load, the word line can be dropped to the unselected level more quickly in the case of non-selection caused by cutting of the fuse element FS. In addition, since the transistor for driving the word line to the non-selection level is removed in normal operation, the capacity is reduced, the access time is shortened, and as the number of transistors is reduced, high density integration can be realized. .

Meanwhile, the present invention is not limited to the above embodiment, but can be applied in various ways. For example, in the above embodiment, the memory device 2 is constituted by an N-channel transistor, but the same can be implemented with the P-channel transistor. Can be. In addition, the load may be divided and connected to the word line in consideration of the case where the word line is cut at a place other than the fuse element FS.

[Effect of design]

As described above, according to the present invention, when the word line is deselected by cutting the fuse element FS, the semiconductor memory is hardly affected by noise or the like because the word line is not floated and is maintained at the non-selected level. Can be provided.

Claims (5)

A first word line WL ₁ directly connected to the memory cell 2, a selection circuit 1 for receiving an address signal, a second word line WL ₂ selected by the selection circuit 1, and A first memory device comprising: a fuse FS connected in series to the first or second word lines WL ₁ and WL ₂ , and a semiconductor memory divided into a plurality of compartments while having a redundancy defective relief cell; A partition address signal SAD is provided between WL ₁ and a second word line WL ₂ to select an arbitrary section from the plurality of sections while the second word line WL ₂ is a first input. A first or second word is cut between the gate circuit 111 serving as a second input, the first or second word lines WL ₁ and WL ₂ , and a power supply terminal or a ground terminal to cut the fuse FS. When the lines WL ₁ and WL ₂ are selected, the loads R, T _P and T _N are maintained to maintain the first or second word lines WL ₁ and WL _{2 at the} unselected voltage level. And a semiconductor memory. The semiconductor memory according to claim 1, wherein said load (R) is made of a resistance element. The semiconductor memory according to claim 1, wherein the loads (T _P , T _N ) are made of MOS transistors. The semiconductor memory according to claim 1, wherein the load (R, T _P , T _N ) is connected to the first or second word lines (WL ₁ , WL ₂ ) at a plurality of places. 2. The semiconductor memory according to claim 1, wherein said gate circuit (111) is a NOR circuit.