JPH03142797A - Redundant circuit for semiconductor memory - Google Patents

Abstract

PURPOSE:To suppress the increase of current consumption caused by short- circuiting between a word line and a bit line by providing a transistor between a precharge activating signal and a GND and further providing a fuse in the precharge activating signal. CONSTITUTION:When a bit line BL1 and a word line WL1 are short-circuited, an NMOS transistor Q2 is turned ON by a precharge signal phi1 and the bit line BL1 is precharged by a precharge power source 1. At such a time, a current flows from a short-circuited part through the word line WL1 and the NMOS transistor Q2 to the GND. However, when a fuse F1 of the defective bit line BL1 is fused, a transistor Q1 for precharge activation is turned OFF by a transistor Q13 and a current path from the precharge power source 1 to the defective bit line is interrupted. Thus, even when the bit line and the word line are short- circuited, the current consumption is not increased.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a redundant circuit for semiconductor memory.

[Conventional technology]

Conventionally, redundant circuits for semiconductor memories include repair word lines and bit lines in order to relieve defective word lines and defective bit lines.

FIG. 2 is a circuit diagram showing a redundant circuit of a conventional semiconductor memory. In FIG. 2, this conventional example has a row (Row)
Word line WLI, bit lines BLI, BLI', and sense amplifier SA1 connected to decoder 2, and word line RWL1 for repair, bit line RBL1, RBLI for repair, and sense amplifier SA1.
It is composed of 2.

Such conventional redundancy circuits
If there is a short circuit between the adjacent word lines or a cell on the word line is defective, the defective word line is not selected and the repair word line R is selected instead.
Select WL1. Or some bit line BLI
, a short between the BLI and its adjacent bit lines,
Or, if a cell on a bit line is defective, do not select that bit line and use the bit line RB for repair.
Select LI and RBLI. In this way, by replacing a defective word line or defective bit line with another spare word line or bit line for repair, a non-defective product is obtained.

[Problem to be solved by the invention]

In the conventional redundant circuit described above, the defective bit line BLI including the sense amplifier is also balanced during the precharge period. Therefore, if the word line WLI and the bit line BLI are short-circuited due to a problem such as a process (10 within the dotted line in FIG. 2), the defective bit line BLI will be connected to the defective word line WL during the precharge period.
A steady current is generated for I, which has the disadvantage of increasing current consumption.

SUMMARY OF THE INVENTION An object of the present invention is to provide a redundant circuit for a semiconductor memory in which the above-mentioned drawbacks are solved and current consumption does not increase even if a bit line and a word line are short-circuited.

[Means to solve the problem]

In the configuration of the redundant circuit of the semiconductor memory of the present invention, a fuse is provided in a MOS transistor that cuts a current path when a word line and a bit line are short-circuited to each other, and a fuse is provided between the fuse and ground. It is characterized by using a MOS transistor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a redundant circuit of a semiconductor memory according to an embodiment of the present invention.

In FIG. 1, the difference between this embodiment and the conventional example is that an NMOS transistor Q is connected to the gate of the N-type field effect transistor Q2 for preventing floating of the bit line BLI.
, and fuse F1. That is, in the redundant circuit of the semiconductor memory of this embodiment, in order to bring the defective bit line replaced by a circuit short between the word line WLI and the bit line BLI into a high impedance state, the gate is connected to the power supply, A transistor Q having a drain connected to the precharge activation signal φ1 and a source connected to the ground, and a fuse F1 for separating the precharge generation source 1 from the precharge activation signal φ1 are provided in the line of the precharge activation signal φ1. Word line WL
At the end of I, between GND and the word line WLI, there is a reset NMOS transistor Q for preventing the word line from floating (preventing a high impedance state).

A reset signal φ2 is input to its gate.

Now, if the bit line BLI and word line WL1 are short-circuited (10 inside the dotted line in Figure 1), the NMOS transistor Q2 is turned on by the precharge signal φ1, and the bit line BLI is pre-charged by the precharge power supply I. Charge. At this time, a current flows from the shorted portion through the word line WLI and through the NMOS transistor Q1 to GND.
If a defect occurs where the defective word line and bit line intersect with the bit line BLI, when replacing the defective word line and bit line with repair word lines and bit lines, if the fuse F1 of the defective bit line BL1 is blown, the transistor Q cuts off the precharge activation transistor Q2, cutting off the current path from the precharge power supply 1 to the defective bit line.

The redundant circuit of this embodiment becomes defective due to a short circuit between the word line and the bit line, which can be repaired.
Although the current consumption still increases even if it is replaced with a word line and a bit line, fuses and transistors are provided to suppress the current consumption.

〔Effect of the invention〕

As explained above, the present invention has a transistor between the precharge activation signal and GND, and further has a fuse in the precharge activation signal to cut off the current path in the event of a short circuit, and connect the word line and bit line. This has the effect of suppressing increases in power consumption due to short circuits with lines.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a redundant circuit of a semiconductor memory according to the present invention, and FIG. 2 is a circuit diagram of a conventional redundant circuit of a semiconductor memory. 1... Precharge power supply, 2... Row decoder, 10...
...Dotted line, SAI. SA2...Sense amplifier, BLI, BLI, R
BLl, RBLI...Bit line, WLI,
RWLl...Word line% Ql, Q2.
Q3...NMOS transistor, φ1...
...Bit line precharge activation signal, Fl...
... Fuse, φ2 ... Reset signal.

Claims (1)

[Claims] A semiconductor memory characterized in that a fuse is provided in a MOS transistor that cuts a current path when a word line and a bit line are short-circuited to each other, and the MOS transistor is interposed between the fuse and ground. redundant circuit.