[go: up one dir, main page]

KR840001369A - 동적 메모리의 리프 레시회로 - Google Patents

동적 메모리의 리프 레시회로 Download PDF

Info

Publication number
KR840001369A
KR840001369A KR1019820003647A KR820003647A KR840001369A KR 840001369 A KR840001369 A KR 840001369A KR 1019820003647 A KR1019820003647 A KR 1019820003647A KR 820003647 A KR820003647 A KR 820003647A KR 840001369 A KR840001369 A KR 840001369A
Authority
KR
South Korea
Prior art keywords
memory
memory access
direct
processing unit
central processing
Prior art date
Application number
KR1019820003647A
Other languages
English (en)
Other versions
KR860000541B1 (ko
Inventor
아더 브류어 제임스 (외 3)
Original Assignee
제이. 에이취. 그레디
인터내쇼날 비지네스 머신즈 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 제이. 에이취. 그레디, 인터내쇼날 비지네스 머신즈 코포레이션 filed Critical 제이. 에이취. 그레디
Publication of KR840001369A publication Critical patent/KR840001369A/ko
Application granted granted Critical
Publication of KR860000541B1 publication Critical patent/KR860000541B1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Bus Control (AREA)

Abstract

내용 없음

Description

동적 메모리의 리프 레시회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
도면은 본 발명의 적합한 실시예를 도시하는 논리 블럭도.

Claims (1)

  1. 시스템 클럭신호를 발생하는 중앙처리장치와, 복수의 우선 순위가 결정된 채널을 가진 프로그램가능한 직접 메모리 액세스 제어장치와, 복수의 입출력장치와, 소정의 시간간격내에서 주기적인 리프레시를 필요로 하는 동적 메모리와의 사이에서 어드레스, 데이타 및 제어정보를 전송하는 시스템 버스를 가진 데이타 처리장치로서, 상기 복수의 채널이, 각기 메모리 어드레스 레지스터 및 카울터, 중앙처리장치/직접 메모리 액세스 싸이클중재회로, 중앙처리장치;직접 메모리 액세스 어드레스 버스멀티 플렉서를 포함하고, 상기 입출력장치가 상기 버스를 거쳐 직접 메모리 액세스 제어장치를 액세스 하는 데이타 처리장치에 있어서, 상기 소정의 시간간격내에서 메모리 리프레시 싸이클을 개시하도록 상기 직접 메모리 액세스 제어장치의 최고의 우선순위의 채널에 메모리 리프레시 요구신호를 주기적으로 인가하기 위하여 중앙처리장치와 직접 메모리 액세스 장치의 최고 우선 순위 채널과의 사이에 접속되어 시스템 클럭신호에 응동하는 메모리 리프레시 요구신호 발생장치를 구비하는 것을 특징으로 하는 동적 메모리의 리프레시 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR8203647A 1981-08-12 1982-08-12 동적 메모리의 리프레시 회로 KR860000541B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US292075 1981-08-12
US292,075 1981-08-12
US06/292,075 US4556952A (en) 1981-08-12 1981-08-12 Refresh circuit for dynamic memory of a data processor employing a direct memory access controller

Publications (2)

Publication Number Publication Date
KR840001369A true KR840001369A (ko) 1984-04-30
KR860000541B1 KR860000541B1 (ko) 1986-05-08

Family

ID=23123091

Family Applications (1)

Application Number Title Priority Date Filing Date
KR8203647A KR860000541B1 (ko) 1981-08-12 1982-08-12 동적 메모리의 리프레시 회로

Country Status (9)

Country Link
US (1) US4556952A (ko)
EP (1) EP0071743A3 (ko)
JP (1) JPS5829197A (ko)
KR (1) KR860000541B1 (ko)
GB (1) GB2103850B (ko)
HK (1) HK72485A (ko)
MX (1) MX153198A (ko)
MY (1) MY8600231A (ko)
PH (1) PH24658A (ko)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4575826A (en) * 1984-02-27 1986-03-11 International Business Machines Corp. Refresh generator system for a dynamic memory
US4703420A (en) * 1985-02-28 1987-10-27 International Business Machines Corporation System for arbitrating use of I/O bus by co-processor and higher priority I/O units in which co-processor automatically request bus access in anticipation of need
CA1240066A (en) * 1985-08-15 1988-08-02 John R. Ramsay Dynamic memory refresh and parity checking circuit
JPS62188096A (ja) * 1986-02-13 1987-08-17 Toshiba Corp 半導体記憶装置のリフレツシユ動作タイミング制御回路
US4924441A (en) * 1987-03-18 1990-05-08 Hayes Microcomputer Products, Inc. Method and apparatus for refreshing a dynamic memory
US5241661A (en) * 1987-03-27 1993-08-31 International Business Machines Corporation DMA access arbitration device in which CPU can arbitrate on behalf of attachment having no arbiter
US4881205A (en) * 1987-04-21 1989-11-14 Casio Computer Co., Ltd. Compact electronic apparatus with a refresh unit for a dynamic type memory
JP2691560B2 (ja) * 1988-05-18 1997-12-17 京セラ株式会社 Ｄ−ｒａｍのリフレッシュ制御方式
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US5247655A (en) * 1989-11-07 1993-09-21 Chips And Technologies, Inc. Sleep mode refresh apparatus
DE69127518T2 (de) * 1990-06-19 1998-04-02 Dell Usa Lp Digitalrechner, der eine Anlage für das aufeinanderfolgende Auffrischen einer erweiterbaren dynamischen RAM-Speicherschaltung hat
US5577214A (en) * 1992-05-18 1996-11-19 Opti, Inc. Programmable hold delay
TW390446U (en) * 1992-10-01 2000-05-11 Hudson Soft Co Ltd Information processing system
US5473770A (en) * 1993-03-02 1995-12-05 Tandem Computers Incorporated Fault-tolerant computer system with hidden local memory refresh
EP0855718A1 (en) * 1997-01-28 1998-07-29 Hewlett-Packard Company Memory low power mode control
US7089344B1 (en) * 2000-06-09 2006-08-08 Motorola, Inc. Integrated processor platform supporting wireless handheld multi-media devices
WO2007003984A1 (en) 2005-06-30 2007-01-11 Freescale Semiconductor, Inc. Device and method for arbitrating between direct memory access task requests
DE602005023542D1 (de) * 2005-06-30 2010-10-21 Freescale Semiconductor Inc Einrichtung und verfahren zum ausführen einer dma-task
JP2009510543A (ja) * 2005-06-30 2009-03-12 フリースケール セミコンダクター インコーポレイテッド Ｄｍａタスクの実行を制御するためのデバイスおよび方法
WO2007003985A1 (en) * 2005-06-30 2007-01-11 Freescale Semiconductor, Inc. Device and method for controlling multiple dma tasks
US7472292B2 (en) * 2005-10-03 2008-12-30 Hewlett-Packard Development Company, L.P. System and method for throttling memory power consumption based on status of cover switch of a computer system
US7159082B1 (en) * 2005-10-03 2007-01-02 Hewlett-Packard Development Company, L.P. System and method for throttling memory accesses
WO2007083197A1 (en) 2006-01-18 2007-07-26 Freescale Semiconductor Inc. Device having data sharing capabilities and a method for sharing data
KR100800384B1 (ko) * 2006-06-20 2008-02-01 삼성전자주식회사 반도체 메모리 장치 및 이에 따른 셀프 리프레쉬 방법
US10447461B2 (en) * 2015-12-01 2019-10-15 Infineon Technologies Austria Ag Accessing data via different clocks

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4142233A (en) 1975-10-30 1979-02-27 Tokyo Shibaura Electric Co., Ltd. Refreshing system for dynamic memory
JPS5255337A (en) * 1975-10-31 1977-05-06 Hitachi Ltd Refresh control system
US4137565A (en) * 1977-01-10 1979-01-30 Xerox Corporation Direct memory access module for a controller
US4218753A (en) * 1977-02-28 1980-08-19 Data General Corporation Microcode-controlled memory refresh apparatus for a data processing system
US4207618A (en) 1978-06-26 1980-06-10 Texas Instruments Incorporated On-chip refresh for dynamic memory
US4185323A (en) 1978-07-20 1980-01-22 Honeywell Information Systems Inc. Dynamic memory system which includes apparatus for performing refresh operations in parallel with normal memory operations
US4317169A (en) * 1979-02-14 1982-02-23 Honeywell Information Systems Inc. Data processing system having centralized memory refresh
JPS55139691A (en) 1979-04-11 1980-10-31 Matsushita Electric Ind Co Ltd Memory circuit control system

Also Published As

Publication number Publication date
MX153198A (es) 1986-08-21
KR860000541B1 (ko) 1986-05-08
MY8600231A (en) 1986-12-31
PH24658A (en) 1990-09-07
HK72485A (en) 1985-10-04
JPS5829197A (ja) 1983-02-21
US4556952A (en) 1985-12-03
EP0071743A2 (en) 1983-02-16
EP0071743A3 (en) 1984-07-25
GB2103850A (en) 1983-02-23
GB2103850B (en) 1985-03-20

Similar Documents

Publication Publication Date Title
KR840001369A (ko) 동적 메모리의 리프 레시회로
KR920006858A (ko) 직접 메모리 억세스 테이타 전송중의 버스 중재 최적화 방법 및 장치
KR950033856A (ko) 데이타 전송 제어방법과 이것에 사용하는 주변회로, 데이타 프로세서 및 데이타 처리 시스템
KR880004380A (ko) 버스트 전송 모드를 갖는 버스 마스터
KR850003008A (ko) 데이타처리 시스템 아키텍처
GB1493818A (en) Information processor input/output
KR860004356A (ko) 데이타 처리장치
KR860003556A (ko) 인터럽트 제어 시스템
KR910012962A (ko) Dma제어기
KR880003252A (ko) 마이크로 프로세서
GB1357028A (en) Data exchanges system
US4575826B1 (ko)
KR850003593A (ko) 악세스 데이타량 및 메모리 대역폭 증가방법
KR860003554A (ko) 공유식 주메모리 및 디스크 제어기 메모리 어드레스 레지스터
KR950023107A (ko) 공용버스에서의 버스점유 중재장치
JPS6478362A (en) One connection preparation of several data processors for central clock control multi-line system
KR860004360A (ko) 원격통신시스템용 마이크로프로세서 인터페이스장치
JPS6326753A (ja) メモリ−バス制御方法
KR960018958A (ko) 다중 프로세서 시스템에서 아토믹 명령어 수행시 데이타 버퍼를 사용한 메인 메모리 액세스 장치
KR970016976A (ko) 동적 메모리 장치를 구비한 시스템의 버스 중재방법 및 회로
SE8001908L (sv) Databehandlingsanleggning
SU1254924A1 (ru) Устройство для управления памятью
KR880011679A (ko) Dma 억세스 중재 장치
Yamaguchi et al. LSI Bubble Memory Controller
KR970029028A (ko) 디지털 시그널 프로세서

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19820812

PA0201 Request for examination
PG1501 Laying open of application
PG1605 Publication of application before grant of patent

Comment text: Decision on Publication of Application

Patent event code: PG16051S01I

Patent event date: 19860411

PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 19860729

PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 19860903

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 19860903

End annual number: 3

Start annual number: 1

PR1001 Payment of annual fee

Payment date: 19890320

Start annual number: 4

End annual number: 4

PC1903 Unpaid annual fee