KR20230151275A - Power semiconductor device, power semiconductor chip including the same, and method for manufacturing the same - Google Patents

Abstract

A power semiconductor device according to an embodiment of the present invention includes gate electrodes, each of which is arranged to be recessed from a first side of a semiconductor substrate toward a second side opposite the first side, the gate electrode An emitter region disposed in contact with each of the trench and the first surface and containing an impurity of a first conductivity type, and a second conductive region disposed in contact with the second surface and having an opposite conductivity type to the first conductivity type. a collector region containing impurities of the second conductivity type, surrounding the bottom surface of the trench and extending toward the second surface along the elongation direction of the trench, and containing impurities of the second conductivity type, within the trench. It may include a trench emitter region disposed between the gate electrodes, and a trench floating region disposed within the trench below the gate electrodes and the trench emitter region.

Description

Power semiconductor device, power semiconductor chip including the same, and method for manufacturing the same {Power semiconductor device, power semiconductor chip including the same, and method for manufacturing the same}

The present invention relates to a power semiconductor device that performs a switching operation, a power semiconductor chip including the same, and a method of manufacturing the same.

A power semiconductor device may refer to a semiconductor device that can perform a switching operation in a high voltage and high current environment. Power semiconductor devices are mainly used in fields (e.g., inverter devices) that require high-power switching (i.e., switching operation in a high voltage and high current environment). Examples of power semiconductor devices include insulated gate bipolar transistors (IGBTs) and power MOSFETs. For these power semiconductor devices, withstand voltage characteristics against high voltage are basically required, and recently, high-speed switching operation is additionally required.

Republic of Korea Publication No. 20140057630 (published May 13, 2014)

The purpose of the present invention is to provide a power semiconductor device that can increase operational stability while securing voltage resistance characteristics against high voltage, a power semiconductor chip including the same, and a method of manufacturing the same.

However, these tasks are illustrative and do not limit the scope of the present invention.

The power semiconductor device according to an embodiment of the present invention for solving the above problem includes gate electrodes each recessed from the first side of the semiconductor substrate toward the second side opposite the first side. , an emitter region disposed in contact with each of the trench in which the gate electrode is disposed and the first surface, and containing an impurity of a first conductivity type, disposed in contact with the second surface, and having an emitter region of the first conductivity type. A collector region containing impurities of a second conductivity type that is of an opposite conductivity type, surrounding the bottom surface of the trench and extending toward the second surface along the elongation direction of the trench, and containing impurities of the second conductivity type. region, a trench emitter region disposed between the gate electrodes within the trench, and a trench floating region disposed below the gate electrodes and the trench emitter region within the trench.

A method of manufacturing a power semiconductor device according to an embodiment of the present invention includes forming a first drift region containing an impurity of a first conductivity type through epitaxial growth, an upper portion of the first drift region forming a floating region by injecting impurities of a second conductivity type that are opposite to the first conductivity type from the first conductivity type, forming a second drift region containing impurities of the first conductivity type on an upper part of the first drift region as epi. Forming through taxial growth, forming an emitter region by injecting an impurity of the first conductivity type from an upper part of the second drift region, and etching at least a portion of the floating region through the emitter region. Forming a trench through etching, forming a trench floating area by depositing a conductive material inside the trench, depositing a conductive material on top of the trench floating area to be spaced apart from the trench floating area to form a gate It may include forming electrodes, and forming a trench emitter region between the gate electrodes by depositing a conductive material to be spaced apart from each of the gate electrodes.

According to the power semiconductor device, the power semiconductor chip including the same, and the manufacturing method thereof according to an embodiment of the present invention, operational stability can be improved while maintaining breakdown voltage characteristics.

This effect is illustrative, and embodiments of the present invention are not limited thereto.

1 is a schematic plan view showing a power semiconductor chip according to an embodiment of the present invention.
FIG. 2 is a diagram briefly showing a power semiconductor chip including the power semiconductor device of FIG. 1.
FIG. 3 is a diagram showing an example of a portion of the cell area shown in FIG. 2.
FIG. 4 is a diagram showing another example of a portion of the cell area shown in FIG. 2.
FIG. 5A is a cross-sectional view of the cell area of FIG. 3 or FIG. 4.
FIG. 5B is an enlarged view of a partial area of FIG. 5A.
FIG. 5C is a graph showing the electric field distribution in the structure shown in FIG. 5A.
6A to 6O are diagrams for explaining a method of manufacturing a power semiconductor device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. The examples below make the disclosure of the present invention complete, and provide those of ordinary skill in the art with the scope of the invention. It is provided to provide complete information. Additionally, for convenience of explanation, the size of at least some components may be exaggerated or reduced in the drawings. In the drawings, like symbols refer to like elements.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by a person of ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for illustrative purposes and thus serve to illustrate the general structures of the present invention.

Identical reference signs indicate identical elements. It will be understood that when one configuration, such as a layer, region, or substrate, is referred to as being on another configuration, it may be in the trench directly above the other configuration, or other intervening configurations in between may also be present. On the other hand, when one designation is referred to as being “directly on” another, it is understood that there are no intervening structures.

1 is a diagram showing an example of a power semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, the power semiconductor device 10 according to an embodiment of the present invention is a device that can be operated as a switch in an environment of high voltage and high current, and can be used, for example, in an inverter.

As shown in FIG. 1, the power semiconductor device 10 may include an insulated gate bipolar transistor (IGBT). According to another embodiment, the power semiconductor device 10 may be implemented with another type of power transistor (e.g., a silicon carbide-based metal oxide semiconductor field effect transistor (MOSFET)), but in the present disclosure, the power semiconductor device 10 The technical idea of the present invention will be explained on the premise that it is implemented as an IGBT.

IGBT may have a structure in which the emitter and collector of a bipolar transistor are combined with the gate of a MOSFET. Accordingly, the power semiconductor device 10 can have both the breakdown voltage characteristics of a bipolar transistor and the relatively fast switching speed of a MOSFET.

IGBT may be a self-extinguishing device in which the gate-emitter voltage (Vge) changes and turns on or off depending on the driving voltage applied to the gate. Here, a self-extinguishing type device may refer to a device that can receive an input signal without relying on an external source and allow current to flow or not flow between two terminals (i.e., emitter and collector) through its own control capability.

The IGBT may include a gate terminal (G) connected to the gate, an emitter terminal (E) connected to the emitter, and a collector terminal (C) connected to the collector. The IGBT is turned on or off depending on the driving voltage input to the gate terminal (G), allowing current to flow or not flow between the emitter terminal (E) and the collector terminal (C). The gate terminal (G) may be connected to a driver circuit (not shown) that transmits the driving voltage, and the emitter terminal (E) and collector terminal (C) may be connected to a load (not shown) to provide a switching function. .

According to one embodiment, the power semiconductor device 10 may further include a freewheeling diode (Df) connected between the emitter terminal (E) and the collector terminal (C). The freewheeling diode (Df) may provide a loop that allows carriers (holes or electrons) accumulated in the emitter or collector due to the on-operation of the IGBT to be emitted again during the off-operation of the IGBT. The freewheeling diode (Df) can prevent impulse voltage by providing this loop, thereby preventing damage to the load connected to the IGBT or power semiconductor device 10.

FIG. 2 is a diagram briefly showing a power semiconductor chip including the power semiconductor device of FIG. 1.

Referring to FIG. 2, the power semiconductor chip 20 may be a semiconductor chip including the power semiconductor device 10 of FIG. 1. The power semiconductor chip 20 may include one power semiconductor device 10 formed integrally, or may include a plurality of power semiconductor devices 10 according to another embodiment.

The power semiconductor chip 20 may include a cell region (100) and a peripheral region (200).

Cell region 100 may include at least one power semiconductor device 10. For example, the arrangement form of the power semiconductor device 10 may correspond to the stripe type of FIG. 3 or the closed type of FIG. 4. This arrangement will be described later with reference to FIGS. 3 and 4.

The cell region 100 may further include an element for monitoring the state of at least one power semiconductor element 10.

According to one embodiment, the cell region 100 may further include a current sensing transistor having a structure substantially the same as that of the power semiconductor device 10 and reduced by a predetermined ratio. As an example, the current sensing transistor may be connected in parallel with the IGBT of the power semiconductor device 10. Here, when connected in parallel, a predetermined resistance may be connected between one terminal of the current sensing transistor and one terminal of the IGBT. The output current of the current sensing transistor (e.g., the output current of the emitter terminal or the collector terminal) has a ratio related to the output current of the power semiconductor device 10 and a predetermined ratio, and through this ratio, the output current of the current sensing transistor is It can be used to indirectly monitor the state of the power semiconductor device 10.

According to another embodiment, the cell region 100 may further include a temperature sensor disposed adjacent to the power semiconductor device 10 to detect the temperature of the power semiconductor device 10. As an example, a temperature sensor may include a junction diode that outputs a current that varies depending on temperature. The current of this junction diode can be used to monitor the temperature of the power semiconductor device 10.

The peripheral area 200 may surround the cell area 100 and may be disposed on the outside of the cell area 100 . The peripheral area 200 may include a plurality of terminals for electrical connection between an external circuit (eg, a driving circuit, a load, a test circuit, etc.) and the cell area 100 . The plurality of terminals may include a gate terminal (G), an emitter terminal (E), and a collector terminal (C) of the IGBT. Additionally, the plurality of terminals may include each terminal of a current sensing transistor and/or a temperature sensor that may be included in the cell region 100.

FIG. 3 is a diagram showing an example of a portion of the cell area shown in FIG. 2.

Referring to Figure 3, a portion 300 of the cell area 100 of Figure 2 is shown. The cell area 100 may have a form in which the parts 300 of the cell area 100 are repeatedly arranged in the up, down, left, and right directions, based on the part 300 of the cell area 100, but within the scope of the present invention. is not limited to this.

A portion 300 of the cell region 100 may include a gate electrode 120, a gate insulating film 122, an emitter region 130, an emitter electrode 132, and a trench emitter region 135.

The gate electrode 120 corresponds to the gate of the IGBT in FIG. 1, and the gate insulating film 122 can electrically separate the gate electrode 120 from other components. The emitter region 130, the emitter electrode 132, and the trench emitter region 135 may correspond to the emitter of the IGBT of FIG. 1.

A portion 300 of the cell region 100 represents a plane corresponding to a specific height in the vertical cross-section of the cell region 100, and the configuration corresponding to the collector of the IGBT in FIG. 1 is a portion 300 of the cell region 100. ) may be located at a different height.

Meanwhile, refer to FIG. 5A for the specific structure, function, and material of each of the gate electrode 120, gate insulating film 122, emitter region 130, emitter electrode 132, and trench emitter region 135. This will be described later. In FIG. 3 , the arrangement form of the gate electrode 120, the gate insulating film 122, the emitter region 130, the emitter electrode 132, and the trench emitter region 135 on a plane will be described.

The gate electrode 120 may be extended along one direction (up and down direction in FIG. 3). The gate insulating film 122 may contact the left or right side of the gate electrode 120 and extend parallel to the gate electrode 120 along one direction.

The emitter region 130 is in contact with the gate insulating film 122 disposed on the left side of the gate electrode 120 or the gate insulating film 122 disposed on the right side of the gate electrode 120 and forms the gate electrode 120 along one direction. It can be stretched parallel to the . That is, the gate insulating film 122 is disposed between the gate electrode 120 and the emitter region 130, and the gate electrode 120 and the emitter region 130 are electrically separated by the gate insulating film 122. You can.

Inside the adjacent gate electrodes 120, a trench emitter region 135 may be disposed to be spaced apart from each of the gate electrodes 120, and each of the gate electrodes 120 and the trench emitter region 135 may be disposed inside the adjacent gate electrodes 120. A gate insulating film 122 is disposed therebetween, so that each of the gate electrodes 120 and the trench emitter region 135 can be electrically separated from each other. The trench emitter region 135 may be extended parallel to each of the gate electrodes 120 .

A trench emitter region 135, gate electrodes 120 disposed on both sides of the trench emitter region 135, an emitter region 130 disposed on the left and right sides of the gate electrode 120, and a gate electrically separating them. Unit cells composed of the insulating film 122 may be arranged at a predetermined distance apart along another direction perpendicular to one direction (left and right directions in FIG. 3). In FIG. 3 , the emitter electrode 132 may be placed in contact with the unit cell on the left and right sides of the unit cell disposed on the left. Additionally, the emitter electrode 132 may be arranged to contact the unit cells on the left and right of the unit cells disposed on the right in FIG. 3 . Accordingly, emitter electrodes 132 may be disposed between unit cells spaced apart in different directions.

Since the unit cell in FIG. 3 has a striped shape, the arrangement form of the power semiconductor device 10 may be defined as a stripe type.

FIG. 4 is a diagram showing another example of a portion of the cell area shown in FIG. 2.

Referring to Figure 4, a portion 400 of the cell area 100 of Figure 2 is shown. The cell area 100 may have a form in which the parts 400 of the cell area 100 are repeatedly arranged in the up, down, left, and right directions, based on the part 400 of the cell area 100, but within the scope of the present invention. is not limited to this.

Since the part 400 of the cell area 100 is substantially the same as the part 300 of the cell area 100 described in FIG. 3 except for the arrangement form, overlapping descriptions will be omitted.

The gate electrode 120 may have a square ring shape. The gate insulating film 122 may contact one side of the gate electrode 120 and extend parallel to the gate electrode 120 .

The emitter region 130 extends parallel to the gate electrode 120 while contacting the gate insulating film 122 disposed on one side of the gate electrode 120 or the gate insulating film 122 disposed on the other side of the gate electrode 120. It can be. That is, the gate insulating film 122 is disposed between the gate electrode 120 and the emitter region 130, and the gate electrode 120 and the emitter region 130 are electrically separated by the gate insulating film 122. You can.

A trench emitter region 135 may be disposed between adjacent gate electrodes 120 and spaced apart from each of the gate electrodes 120, and each of the gate electrodes 120 and the trench emitter region 135 may be disposed between adjacent gate electrodes 120. A gate insulating film 122 is disposed therebetween, so that each of the gate electrodes 120 and the trench emitter region 135 can be electrically separated from each other. The trench emitter region 135 may be extended parallel to each of the gate electrodes 120 .

Trench emitter region 135, gate electrodes 120 surrounded by or surrounding trench emitter region 135, gate electrodes 120 or gate electrodes ( A unit cell composed of emitter regions 130 surrounding the emitter regions 120 and a gate insulating film 122 electrically separating them may have an overall rectangular ring shape.

In FIG. 4 , emitter electrodes 132 may be disposed on each inside and outside of the unit cell to be in contact with the unit cell.

In that the unit cell in FIG. 4 has a ring shape, the arrangement form of the power semiconductor device 10 may be defined as a closed type.

The striped type shown in Figure 3 is advantageous in terms of the static characteristics of the IGBT as it can implement a relatively high channel density (density of channels between emitter and collector), and the closed type shown in Figure 4 has the size and ratio of parasitic capacitance. can be adjusted more easily, which can be advantageous in terms of switching stability of the IGBT. Depending on the purpose and requirements of the IGBT, a striped type or closed type can be selected.

According to another embodiment, the cell area 100 may be implemented as a ladder type, which is a combination of a stripe type and a closed type. In the leather type, the gate electrode 120 is extended at a predetermined distance along one direction like the stripe type, but the gate electrode 120 is extended in a direction perpendicular to one direction, corresponding to the stripe type. ) can refer to a form that connects etc. The leather type can have the advantages of both the striped type and the closed type.

FIG. 5A is a cross-sectional view of the cell area of FIG. 3 or FIG. 4. FIG. 5B is an enlarged view of a partial area of FIG. 5A. FIG. 5C is a graph showing the electric field distribution in the structure shown in FIG. 5A.

Referring to FIG. 5A, a cross section 500 is shown by cutting the cell area 100 along the first line (A-A') of FIG. 3 or the second line (BB') of FIG. 4, The first line (A-A') or the second line (B-B') may correspond to the third line (C-C') in FIG. 5A.

The cross section 500 includes a semiconductor substrate 110, a collector electrode 112 disposed below the semiconductor substrate 110, a gate insulating film 122 at least partially protruding from the top of the semiconductor substrate 110, and an emitter electrode ( 132) may be included.

The semiconductor substrate 110 may refer to at least one semiconductor material layer (eg, an epitaxial layer). For example, the semiconductor substrate 110 may include a semiconductor material such as silicon, germanium, or silicon-germanium. The semiconductor substrate 110 may refer to an area from the third line C-C' to the bottom of the collector electrode 112.

The semiconductor substrate 110 includes a collector region (114), a drift region (116), a well region (118), a gate electrode (120), and a gate insulating film (122). ), an emitter region (130), a portion of an emitter electrode (132), a trench emitter region (135), a trench floating region (140) and floating It may contain a floating region (150). The semiconductor substrate 110 may include an upper surface (or first surface) and a lower surface (or second surface) opposing the upper surface.

The collector region 114 may include impurities having a second conductivity type. The second conductivity type may be P-type or N-type, and the second conductivity type may be the opposite conductivity type of the first conductivity type. The collector region 114 may be formed to have a predetermined thickness while being in contact with the lower surface of the semiconductor substrate 110 . The collector area 114 may be disposed to contact the lower collector electrode 112. The collector electrode 112 may be electrically connected to the collector terminal C of FIG. 1 and may include at least one of polysilicon, metal, metal nitride, and metal silicide.

The collector area 114 and the collector electrode 112 may correspond to the collector of the IGBT in FIG. 1.

The drift region 116 may include impurities having a first conductivity type. The first conductivity type may be P-type or N-type, and the first conductivity type may be the opposite conductivity type of the second conductivity type. The drift region 116 may provide a vertical movement path for charges (holes and electrons) between the collector region 114 and the emitter region 130. The drift area 116 is disposed on the upper part of the collector area 114, touches each side of the floating area 150 and the trench TH, and extends along the elongation direction of the trench TH (up and down direction in FIG. 5A). It can be.

The well region 118 may include impurities having a second conductivity type. The well region 118 may be disposed between the drift region 116 and the emitter region 130 and between the drift region 116 and the emitter electrode 132. Additionally, the well region 118 may be located between adjacent trenches (TH) in which the gate electrode 120 and the gate insulating layer 122 are respectively disposed. The well region 118 may be disposed to contact the drift region 107, the gate insulating film 122, the emitter region 130, and the emitter electrode 132, respectively. The trench TH may refer to a structure recessed to a predetermined depth from one side of the semiconductor substrate 110 toward the other side of the semiconductor substrate 110.

The depth from the top surface of the semiconductor substrate 110 to the bottom surface of the well region 118 may be shallower than the depth from the top surface of the semiconductor substrate 110 to the bottom surface of the trench TH.

The gate electrode 120 may include at least one of a conductive material, for example, polysilicon, metal, metal nitride, and metal silicide. The gate electrode 120 may be disposed to fill the inside of the trench TH while contacting the gate insulating film 122 inside the trench TH. Accordingly, the gate electrode 120 may be recessed to a predetermined depth from the upper surface of the semiconductor substrate 110 to the lower surface of the semiconductor substrate 110 .

The gate electrode 120 may be formed of two parts separated from each other within the trench TH. That is, the trench emitter region 135 may be disposed in the center of the trench TH, and each of the gate electrodes 120 may be disposed on both left and right sides of the trench emitter region 135.

The gate electrode 120 may extend parallel to the trench emitter region 135 from the top surface of the semiconductor substrate 110 toward the bottom surface of the semiconductor substrate 110 . The length that the gate electrode 120 extends from the top surface of the semiconductor substrate 110 may be smaller than the length that the trench emitter region 135 extends from the top surface of the semiconductor substrate 110, but the scope of the present invention is not limited thereto. No.

The gate electrode 120 may correspond to the gate of the IGBT of FIG. 1 and may be electrically connected to the gate terminal (G) of FIG. 1.

The gate insulating film 122 may include at least one of an insulating material, for example, silicon oxide, silicon nitride, germanium oxide, germanium nitride, hafnium oxide, zirconium oxide, and aluminum oxide. The gate insulating film 122 may be disposed along the side of the trench TH and in contact with the gate electrode 120 inside the trench TH. Additionally, the gate insulating film 122 may extend outside the semiconductor substrate 110 and be disposed on top of the gate electrode 120, the emitter region 130, and the trench emitter region 135. The gate insulating layer 122 extending outside of the semiconductor substrate 110 may be called an interlayer insulating layer.

The gate insulating film 122 located inside the trench TH is between the surface of the trench TH and the gate electrode 120, between the surface of the trench TH and the trench floating area 140, and between the gate electrode 120 and the gate electrode 120. It may be disposed between the trench emitter region 135 and between the region where the gate electrode 120 and the trench emitter region 135 are located (i.e., the upper region) and the trench floating region 140.

The gate insulating film 122 may electrically separate the gate electrode 120 from each of the drift region 116, the well region 118, the emitter region 130, the emitter electrode 132, and the floating region 150. there is. Additionally, the gate insulating layer 122 may electrically separate the gate electrode 120, the trench emitter region 135, and the trench floating region 140 from each other.

The emitter region 130 may include impurities having a first conductivity type. The impurity doping concentration of the first conductivity type in the emitter region 130 may be higher than the impurity doping concentration of the first conductivity type in the drift region 116 . The emitter region 130 is in contact with the upper surface of the semiconductor substrate 110 and has a gate insulating film 122 (or trench (TH)) between the gate insulating film 122 of the trench (TH) and the emitter electrode 132. It may be placed in contact with each of the emitter electrodes 132. Additionally, the lower surface of the emitter region 130 may be disposed to contact the well region 118. The emitter region 130 may be disposed on one side and the other side (or both left and right sides) of the trench TH.

The emitter electrode 132 may include at least one of a conductive material, for example, polysilicon, metal, metal nitride, and metal silicide. The emitter electrode 132 is arranged to cover the upper part of the semiconductor substrate 110 while contacting the gate insulating film 122, the well region 118, and the emitter region 130 that protrude to the outside of the semiconductor substrate 110. You can.

The emitter electrode 132 acts as a contact with the well region 118 and applies a low voltage lower than the voltage on the collector side of the IGBT to the well region 118, and the emitter region 130 It can function as an electrode that electrically connects the emitter region 130 and the emitter terminal (E) of FIG. 1. The emitter area 130 and the emitter electrode 132 may correspond to the emitter of the IGBT in FIG. 1.

The trench emitter region 135 may include at least one of a conductive material, for example, polysilicon, metal, metal nitride, and metal silicide. The trench emitter region 135 may be disposed between the gate electrodes 120 and above the trench floating region 140 . Additionally, the trench emitter region 135 may be disposed to contact the gate insulating layer 122 and be electrically isolated from the gate electrodes 120 and the trench floating region 140 .

The trench emitter region 135 may extend parallel to the gate electrode 120 from the top surface of the semiconductor substrate 110 toward the bottom surface of the semiconductor substrate 110 . The length that the trench emitter region 135 extends from the top surface of the semiconductor substrate 110 may be greater than the length that the gate electrode 120 extends from the top surface of the semiconductor substrate 110, but the scope of the present invention is not limited thereto. No.

The trench emitter region 135 may be electrically connected to the emitter electrode 132 and may correspond to the emitter of the IGBT of FIG. 1 together with the emitter region 130 electrically connected to the emitter electrode 132. there is. A contact hole is formed in which at least a portion of the gate insulating film 122 on the trench emitter region 135 is omitted at a random location (not shown) in the cell region 100 or the peripheral region 200, The trench emitter region 135 may be electrically connected to the emitter electrode 132 through a contact hole, but the scope of the present invention is not limited thereto.

The trench floating region 140 may include at least one of a conductive material, for example, polysilicon, metal, metal nitride, and metal silicide. The trench floating area 140 may be an electrically floating area to which no bias voltage is applied from the outside.

The trench floating region 140 is disposed below the gate electrodes 120 and the trench emitter region 135, and conducts electrical energy from the gate electrodes 120 and the trench emitter region 135 by the gate insulating film 122. can be separated. The trench floating area 140 is arranged to be in contact with the gate insulating film 122 disposed between the bottom and side surfaces of the trench TH, and includes a surface corresponding to the shape of the bottom and side surfaces of the trench TH. can do.

The floating area 150 may include impurities having a second conductivity type. The floating area 150 may be an electrically floating area to which no bias voltage is applied from the outside.

The floating area 150 may surround the bottom surface of the trench TH and extend toward the collector area 114 along the extension direction of the trench TH (up and down direction in FIG. 5A).

The floating area 150 may have a width W wider than the width W' of the trench TH so as to entirely surround the bottom surface of the trench TH. If the floating area 150 is not included, the electric field may be concentrated on the bottom surface of the trench TH when the IGBT operates, and the maximum electric field may be formed on the bottom surface of the trench TH. Since the thickness of the gate insulating layer 122 is only about a few hundred nm, the breakdown voltage of the IGBT may be lowered as the electric field is concentrated on the bottom surface of the trench TH. This drop in breakdown voltage may make normal switching operation of the IGBT impossible. However, when the floating area 150 entirely surrounds the bottom surface of the trench TH as in the present disclosure, the electric field is not concentrated on the bottom surface of the trench TH through a charge sharing phenomenon and the floating area 150 ), the electric field is distributed and the maximum electric field can be formed on the bottom surface of the floating area 150. Therefore, the switching performance of the IGBT can be secured without a decrease in the breakdown voltage of the IGBT. That is, due to the floating area 150, the IGBT can perform a switching operation even in a high voltage environment, thereby improving withstand voltage characteristics. In addition, the gate insulating film 122 located below the gate electrode 120 has a thicker thickness than the gate insulating film 122 located on the side of the gate electrode 120, so the electric field is concentrated on the bottom surface of the trench TH. This phenomenon can be further prevented.

Additionally, the trench floating region 140 included in the trench TH may increase the breakdown voltage of the IGBT by further strengthening the charge sharing phenomenon in its relationship with the drift region 116.

Referring to FIG. 5C, an example of an electric field distributed along a straight line (D-D') shown in FIG. 5A is shown. The first electric field (EF_P) represents an example of an electric field distributed along the straight line (D-D') shown in FIG. 5A, and the second electric field (EF_C) represents an example of an electric field distributed along the straight line (D-D') shown in FIG. 5A, where the trench floating area 140 is omitted from the structure of FIG. 5A. An example of the electric field at a position corresponding to the straight line (D-D') in the structure (i.e., comparative example of the present invention) can be shown.

As the electric field is dispersed due to the charge sharing phenomenon by the trench floating region 140, the first electric field EF_P may have a higher overall electric field intensity than the second electric field EF_C. Accordingly, the area of the first electric field (EF_P) may be larger than the area of the second electric field (EF_C). Here, the area of the first electric field (EF_P) or the second electric field (EF_C) may mean a value obtained by integrating the intensity of the electric field along the straight line (D-D'). Additionally, the area of the first electric field (EF_P) or the second electric field (EF_C) may indicate the size of the breakdown voltage of the IGBT, and the breakdown voltage of the IGBT having the structure of FIG. 5A including the trench floating area 140 is the trench It may be greater than the breakdown voltage of an IGBT having a structure that does not include the floating area 140.

Referring again to FIG. 5A, the bottom surface of the trench TH may have an overall rounded shape so that there is no angled area in the portion extending from the bottom surface of the trench TH to the side of the trench TH. there is. If an angled area exists in the lower part of the trench TH, the breakdown voltage of the IGBT may be lowered as the electric field is concentrated in the angled area. Accordingly, the trench TH according to the present disclosure may have an overall rounded bottom surface to improve voltage resistance characteristics.

The width W of the floating area 150 may be larger than the width W' of the trench TH, but may be determined to have only a difference sufficient to entirely surround the bottom surface of the trench TH. That is, the width W of the floating area 150 may have a value very close to the width W' of the trench TH. Accordingly, one unit consisting of the trench TH and the floating area 150 surrounding the lower portion of the trench TH may have a relatively narrow width W, and the gap between adjacent gate electrodes 120 may be small. Since the pitch can be reduced, the element density of the cell area 100 can be increased.

When the IGBT operates, a charge transfer path between the collector and the emitter is formed in the drift region 116 between adjacent gate electrodes 120 and between adjacent floating regions 150. When the gap between (120) and adjacent floating areas 150 is narrowed, the density of the channel between the collector and emitter increases, the gain of the IGBT increases, and carrier movement between the collector and emitter becomes easier. JFET resistance can be reduced, which can improve switching performance. However, if the gap between adjacent gate electrodes 120 and adjacent floating regions 150 is excessively narrowed, the area of the charge transfer path will also be narrowed, which may increase the turn on resistance of the IGBT. You can. In particular, if the gap between adjacent floating regions 150 is excessively narrowed, the area of the charge movement path will be further narrowed due to the depletion region formed by the junction between the floating region 150 and the drift region 116. You can. Since an increase in the turn-on resistance of the IGBT may reduce the switching speed of the IGBT, a drift region 116 (i.e., a floating region ( The impurity doping concentration of the first conductivity type in the drift region on the upper side of the virtual straight line parallel to one surface of the semiconductor substrate 150 while passing through the bottom of the semiconductor substrate 150 is calculated as the drift region 116 below the floating regions 150. Turn-on of the IGBT by relatively increasing the impurity doping concentration of the first conductivity type in the drift region below the virtual straight line parallel to one surface of the semiconductor substrate 150 while passing through the bottom of the floating region 150. Resistance can be lowered.

The floating area 150 may have a length L extending from the top of the floating area 150 to the bottom of the floating area 150 along the extension direction of the trench TH. The top of the floating area 150 may be shallower than the bottom of the trench TH and deeper than the bottom of the well area 118 from the top surface of the semiconductor substrate 110 . Additionally, the bottom of the floating area 150 may be deeper than the top of the collector area 114 from the bottom of the semiconductor substrate 110 . That is, the bottom of the floating area 150 and the top of the collector area 114 may be spaced apart from each other by a predetermined distance.

The length (L) of the floating area 150 may be greater than the width (W) of the floating area 150 and may be determined to have as large a value as possible. By forming the floating area 150 as long as possible, the position of the maximum electric field can be adjusted as close as possible to the collector area 114 in FIG. 5A, which increases the breakdown voltage and improves the breakdown voltage characteristics.

Referring again to FIG. 5B, an enlarged view of a portion 550 of FIG. 5A is shown. A first gate-emitter parasitic capacitance Cge1 may occur at the interface between the gate electrode 120 and the well region 118 disposed on one side (left or right) of the gate electrode 120. In addition, a second parasitic capacitance (Cge1) between the gate and emitter may occur at the interface between the gate electrode 120 and the trench emitter region 135 disposed on one side (right or left) of the gate electrode 120. there is. In addition, gate-collector parasitic capacitance (Cgc) may occur at the interface between the gate electrode 120 and the drift region 116 disposed on the left and right sides of the gate electrode 120.

The overall gate-emitter parasitic capacitance (Cge) of the IGBT is the first parasitic capacitance (Cge1) occurring between the gate electrode 120 and the emitter region 130, and the gate electrode 120 and the trench emitter region ( 135), it may be the sum of the second parasitic capacitance (Cge2) occurring between them. That is, since the trench emitter region 135 also exists inside the trench (TH), the parasitic capacitance (Cge) between the gate and emitter is relatively very high (about twice) compared to when only the emitter region 130 exists. It can happen.

As the parasitic capacitance (Cge) between the gate and emitter increases, the stability of the switching operation may increase, but the switching speed may decrease, so the gate insulating film 122 is adjusted so that the parasitic capacitance (Cge) between the gate and emitter has an appropriate value. Thickness, doping concentration of the well region 118 and emitter region 130, shape/material of the trench emitter region 135, etc. may be adjusted.

As shown in FIG. 5A, the gate insulating film 122 located between the gate electrode 120 and the well region 118 and between the gate electrode 120 and the trench emitter region 135 has a relatively thin thickness. , the parasitic capacitance (Cge) between the gate and emitter may have a relatively large value.

The overall gate-collector parasitic capacitance (Cgc) of the IGBT is the parasitic capacitance occurring at the interface between the gate electrode 120 and the left and right drift areas 116, the bottom surface of the floating area 150, and the drift area 116. It may be the sum of parasitic capacitances occurring at the interface between them. Of course, parasitic capacitance may occur in other areas, but the explanation will focus on the main parasitic capacitance. Here, the size of the parasitic capacitance occurring at the interface between the bottom surface of the floating area 150 and the drift area 116 decreases as the distance between the bottom surface of the gate electrode 120 and the bottom surface of the floating area 150 increases. You can lose. That is, assuming that the top depth of the floating area 150 is fixed, as the length (L) of the floating area 150 increases, the parasitic capacitance (Cgc) between the gate and collector of the IGBT may decrease.

Additionally, the size of the parasitic capacitance occurring at the interface between the gate electrode 120 and the left and right drift regions 116 may decrease as the thickness of the gate insulating film 122 disposed below the gate electrode 120 increases. . In other words, as the length of the gate electrode 120 extending from the upper surface of the semiconductor substrate 110 toward the lower surface of the semiconductor substrate 110 becomes shorter, the distance between the gate electrode 120 and the drift area 116 on the left and right increases. The size of parasitic capacitance occurring at the interface can be reduced. For example, the distance between the gate electrode 120 and a random point of the drift region 116 adjacent to the top of the floating region 150 is such that the gate electrode 120 is separated from the upper surface of the semiconductor substrate 110. As the length extending toward the bottom of the increases, the size of the parasitic capacitance may decrease. Additionally, the gate electrode 120 has a shape whose width gradually narrows toward the bottom, and the thickness of the gate insulating film 122 between the gate electrode 120 and the drift region 116 may gradually increase. Due to this increase in the thickness of the gate insulating film 122, the size of the parasitic capacitance occurring at the interface between the gate electrode 120 and the left and right drift regions 116 may become smaller. In order to reduce the parasitic capacitance (Cgc) between the gate and collector, the gate electrode 120 may have a length as short as possible. However, the gate electrode 120 has a shape that is biased toward the trench emitter region 135 toward the bottom of the gate electrode 120, and the trench emitter region 135 has a longer length than the gate electrode 120, thereby forming a gate -The parasitic capacitance (Cge) between emitters may increase.

Accordingly, the parasitic capacitance (Cgc) between the gate and the collector can be adjusted by adjusting at least one of the depth at which the floating region 150 is formed, the shape of the gate electrode 120, or the thickness of the gate insulating film.

In a power semiconductor device having a trench-type gate structure as shown in FIG. 5A, when carriers (e.g., holes) are excessively accumulated at the interface of the trench TH, a negative gate capacitance (NGC) phenomenon occurs, resulting in displacement current. may occur. This displacement current can impair the stability of the switching operation of the IGBT and has characteristics proportional to the size of the parasitic capacitance (Cgc) between the gate and collector.

According to the present disclosure, by adjusting at least one of the depth at which the floating region 150 is formed, the shape of the gate electrode 120, or the thickness of the gate insulating film, the parasitic capacitance (Cgc) between the gate and collector is adjusted to perform the necessary switching operation. Stability can be satisfied.

The switching loss and switching operation stability of an IGBT can depend on the capacitance ratio (Cge/Cgc) between the gate-to-emitter parasitic capacitance (Cge) and the gate-to-collector parasitic capacitance (Cgc), and the capacitance ratio (Cge/Cgc) The higher the value, the lower the switching loss and the higher the stability of switching operation.

When the IGBT is turned on, the turn-on resistance, which is the ratio of the voltage between the collector and the emitter (Vce) and the current between the collector and the emitter (Ice), can indicate the size of the switching loss of the IGBT. In other words, the lower the turn-on resistance, the lower the switching loss of the IGBT. Additionally, the turn-on resistance may depend on the capacitance ratio (Cge/Cgc), and according to a structure that relatively increases the capacitance ratio (Cge/Cgc) as shown in Figure 5a, the turn-on resistance can be lowered, and thus the IGBT's Switching losses can be reduced.

Among the characteristics of the IGBT in a short circuit state, the degree to which overshooting of the voltage (Vge) between the gate and emitter occurs when the IGBT is turned on can indicate the stability of the switching operation of the IGBT. In other words, the lower the degree of overshooting of the gate-emitter voltage (Vge), the higher the switching operation stability can be. In addition, the degree to which overshooting of the gate-emitter voltage (Vge) occurs may depend on the capacitance ratio (Cge/Cgc), and a structure that relatively increases the capacitance ratio (Cge/Cgc) as shown in Figure 5a. According to this, the degree to which overshooting of the gate-emitter voltage (Vge) occurs can be reduced, and thus the stability of the switching operation of the IGBT can be increased.

6A to 6O are diagrams for explaining a method of manufacturing a power semiconductor device according to an embodiment of the present invention.

Referring to FIGS. 6A to 6O , in step S10, a structure in which a drift region 116' is stacked on top of the collector electrode 112 and the collector region 114 may be provided. Here, the drift area 116' may have a lower height than the drift area 116 shown in FIG. 5A. The drift region 116' may be formed through epitaxial growth. In the present disclosure, the description is made assuming that the collector electrode 112 and the collector region 114 have already been formed below the drift region 116' in step S10, but at least one of the collector electrode 112 and the collector region 114 One may be formed after the S10 stage.

In step S20, a photoresist pattern defining the floating area 150 is placed on the upper part of the drift area 116', and an impurity having a second conductivity type is injected from the upper part of the drift area 116'. Thus, the floating area 150 can be formed. The energy for injecting the impurity having the second conductivity type may be determined so that the length (L) of the floating region 150 satisfies a predetermined capacitance ratio (Cge/Cgc).

In step S30, the drift region 116 may be formed by adding an epitaxial layer having a first conductivity type through epitaxial growth on the upper part of the drift region 116' (i.e., the upper side of the boundary BD). . That is, the drift area 116 includes a drift area 116' formed before the formation of the floating area 150 (or a first drift area located below the boundary BD), and a drift area 116' formed before the formation of the floating area 150. It may include a formed drift area (or a second drift area located above the boundary BD). In the present disclosure, the drift area 116 is first formed as a whole, and then the floating area 150 located inside the drift area 116 is not formed through processes such as etching, photoresist, and polishing, but the drift area 116 is formed. By inserting the implantation process of the floating region 150 in the middle of the epitaxial growth for , the floating region 150 can be formed to a depth that cannot be formed with general injection equipment.

In step S40, the well region 118 is formed by injecting impurities having a second conductivity type overall into the upper part of the drift region 116, and then the emitter region 130 is defined on the upper part of the drift region 116. The emitter region 130 may be formed by placing a photoresist pattern and injecting an impurity having a first conductivity type from the top of the drift region 116.

In step S50, an etching mask defining a trench (TH) is placed on the top of the well region 118 and the emitter region 130, and the well region 118 and the emitter region 130 are etched. ) can form a trench (TH) penetrating. The trench TH may be formed at a position corresponding to the floating area 150 to a depth capable of etching at least a portion of the floating area 150 and with a width W' narrower than the width W of the floating area 150. You can.

In step S60, an insulating material (e.g., silicon oxide) is isotropically deposited entirely on the surfaces of the trench (TH), the well region 118, and the emitter region 130 to form the first surface insulating layer 123. can do. The trench floating region 140 may be formed by anisotropically depositing a conductive material (eg, polysilicon) at a predetermined height on the first surface insulating layer 123 . Accordingly, a conductive material layer 142 may be formed on top of the well region 118 and the emitter region 130.

In step S70, an intermediate insulating layer 124 may be formed by depositing an insulating material (eg, silicon oxide) on top of the trench floating region 140 and the conductive material layer 142. Additionally, the protective film 125 may be formed by isotropically depositing an insulating material (eg, silicon nitride) inside the trench TH and then performing anisotropic etching. The protective film 125 may protect the first surface insulating layer 123 inside the trench TH and act as a mask to guide the etched position in the subsequent etching process.

In step S80, the intermediate insulating layer 124 may be etched to a predetermined depth using the protective film 125 as a mask to form the etched intermediate insulating layer 124'. The depth at which the middle insulating layer 124 is etched may be the same as the depth from the bottom of the gate electrode 120 to the bottom of the trench emitter region 135 in FIG. 5A.

In step S90, the protective film 125 is removed and then a conductive material (eg, polysilicon) is isotropically deposited to form the electrode layer 120'.

In step S100, the gate electrode 120 may be formed by anisotropically etching the electrode layer 120', and an insulating material (eg, silicon oxide) may be entirely deposited to form the second surface insulating layer 126.

In step S110, the trench emitter region 135 may be formed by gap-filling a conductive material (eg, polysilicon) inside the trench TH.

In step S120, components located higher than the height corresponding to the top of the emitter region 130 may be removed through a polishing process to flatten the upper part of the semiconductor substrate 110. Accordingly, the upper portions of each of the emitter region 130, the gate electrode 120, and the trench emitter region 135 may be exposed. The first and second surface insulating layers 123 and 126 and the middle insulating layer 124' after the polishing process may be displayed as one gate insulating film 122'.

In step S130, the upper insulating layer 128 may be applied on top of the semiconductor substrate 110. The upper insulating layer 128 may have the same material as the gate insulating layer 122' described above.

In step S140, an etching mask may be placed on the upper insulating layer 128, and a vacancy (VC), which is an empty space, may be formed through etching. The position of the etching mask and the etching depth may be determined in advance so that the emitter region 130 can be exposed by etching. At least a portion of the emitter region 130 and the well region 118 may be exposed through etching. Additionally, the gate insulating layer 122' and the etched upper insulating layer 128 may integrally have the shape of the gate insulating layer 122 shown in FIG. 5A.

In step S150, a conductive material is gap-filled and applied to the top and cavity (VC) of the gate insulating film 122 to form the emitter electrode 132, thereby forming the structure of the power semiconductor device 10 shown in FIG. 5A. can be formed.

The present invention has been described with reference to the embodiments shown in the drawings, but these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the attached patent claims.

Claims (16)

gate electrodes each of which is recessed from a first side of the semiconductor substrate toward a second side opposite the first side;
an emitter region disposed in contact with each of the first surface and the trench in which the gate electrode is disposed, and including an impurity of a first conductivity type;
a collector region disposed in contact with the second surface and including an impurity of a second conductivity type that is opposite to the first conductivity type;
a floating region that surrounds the bottom surface of the trench and extends toward the second surface along the elongation direction of the trench, and includes impurities of the second conductivity type;
a trench emitter region disposed between the gate electrodes within the trench; and
A power semiconductor device comprising a trench floating region disposed below the gate electrodes and the trench emitter region within the trench. According to paragraph 1,
A power semiconductor device further comprising a gate insulating film disposed between each of the gate electrodes and the trench emitter region, and between each of the gate electrodes and the trench floating region. According to paragraph 1,
The length that the trench emitter region extends from the first side of the semiconductor substrate is longer than the length that each of the gate electrodes extends from the first side. According to paragraph 1,
A power semiconductor device wherein the trench emitter region is electrically connected to the emitter region through an emitter electrode. According to paragraph 1,
A semiconductor device wherein each of the trench emitter region and the trench floating region includes polysilicon. According to paragraph 1,
A semiconductor device in which the trench floating region is electrically floating. According to paragraph 1,
A power semiconductor device wherein the length of the floating area along the stretching direction is greater than the width of the floating area. According to paragraph 1,
A power semiconductor device wherein the width of the floating area is greater than the width of the trench. According to paragraph 1,
A power semiconductor device wherein the depth of the top of the floating area from the first surface is shallower than the depth of the bottom of the trench from the first surface. According to paragraph 1,
A power semiconductor device wherein the bottom of the floating area and the top of the collector area are spaced apart from each other by a predetermined distance. According to paragraph 1,
The emitter region is a power semiconductor device disposed on one side and the other side of the trench, respectively. According to paragraph 1,
A power semiconductor device disposed on an upper portion of the collector region, extending along the elongation direction while contacting each side of the floating region and the trench, and further comprising a drift region including an impurity of the first conductivity type. According to clause 12,
A power semiconductor device wherein an impurity doping concentration of the first conductivity type in the emitter region is higher than an impurity doping concentration of the first conductivity type in the drift region. According to paragraph 1,
A power semiconductor device in which the gate electrode is arranged in a striped or ring shape on a plane. A cell region including the power semiconductor device of claim 1; and
A power semiconductor chip comprising a peripheral region including a gate terminal, an emitter terminal, and a collector terminal electrically connected to each of the gate electrode, the emitter region, and the collector region. forming a first drift region containing impurities of a first conductivity type through epitaxial growth;
forming a floating region by injecting impurities of a second conductivity type, which is an opposite conductivity type of the first conductivity type, from an upper portion of the first drift region;
forming a second drift region containing impurities of the first conductivity type on an upper part of the first drift region through epitaxial growth;
forming an emitter region by injecting impurities of the first conductivity type from an upper part of the second drift region;
forming a trench through the emitter region through etching to etch at least a portion of the floating region;
forming a trench floating area by depositing a conductive material inside the trench;
forming gate electrodes by depositing a conductive material on an upper part of the trench floating area to be spaced apart from the trench floating area; and
A method of manufacturing a power semiconductor device comprising forming a trench emitter region between the gate electrodes by depositing a conductive material to be spaced apart from each of the gate electrodes.

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