KR20210056147A - Power semiconductor device - Google Patents

Abstract

A power semiconductor device according to an aspect of the present invention includes a semiconductor layer, at least one trench formed by being recessed from a surface of the semiconductor layer by a predetermined depth into the semiconductor layer, and the semiconductor at one side of the at least one trench. A well region defined in a layer, a floating region defined in the semiconductor layer on the other side of the at least one trench, and a portion formed on a sidewall of the at least one trench, wherein a thickness of a portion adjacent to the floating region is adjacent to the well region And a gate insulating layer including a sidewall portion thicker than the thickness of and a gate electrode layer formed on the gate insulating layer to fill the at least one trench.

Description

Power semiconductor device

The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device for switching power transmission.

Power semiconductor devices are semiconductor devices that operate in a high voltage and high current environment. Such power semiconductor devices are used in fields requiring high power switching, for example, inverter devices. For example, the power semiconductor device may include an insulated gate bipolar transistor (IGBT), a power MOSFET, and the like. Such a power semiconductor device is basically required to withstand voltage characteristics for a high voltage, and recently, additionally, a high-speed switching operation is required.

Such a semiconductor device operates while electrons injected from a channel and holes injected from a collector flow. However, in the trench gate type power semiconductor device, when holes are excessively accumulated in the trench gate, a negative gate charging (NGC) phenomenon occurs and a displacement current is generated in the gate direction.

In this case, as shown in FIG. 10, the gate-emitter potential (Vge) is instantaneously increased during the switching operation and the collector-emitter current (Ice) is increased, resulting in oscillation and/or overshooting of these values. Can be.

Republic of Korea Publication No. 20140057630 (released on May 13, 2014)

The present invention has been made to solve the above-described problems, and an object thereof is to provide a power semiconductor device capable of suppressing a negative gate charging phenomenon.

However, these problems are exemplary, and the scope of the present invention is not limited thereby.

A power semiconductor device according to an aspect of the present invention for solving the above problems includes a semiconductor layer, at least one trench formed by being recessed from a surface of the semiconductor layer by a predetermined depth into the semiconductor layer, and the at least one A well region defined in the semiconductor layer at one side of the trench, a floating region defined in the semiconductor layer at the other side of the at least one trench, and a thickness of a portion adjacent to the floating region formed on a sidewall of the at least one trench And a gate insulating layer including a sidewall portion thicker than a thickness of a portion adjacent to the well region, and a gate electrode layer formed on the gate insulating layer to fill the at least one trench.

According to the power semiconductor device, the gate insulating layer may further include a lower buried portion filling a lower portion of the at least one trench, and the sidewall portion may be formed on the lower buried portion.

According to the power semiconductor device, a thickness of the lower buried portion may be thicker than a thickness of the sidewall portion.

According to the power semiconductor device, the semiconductor layer may be doped with an impurity of a first conductivity type, and the well region and the floating region may be doped with an impurity of a second conductivity type opposite to the first conductivity type.

According to the power semiconductor device, the at least one trench may include at least a pair of trenches extending in a stripe type, and the well region may be formed in the semiconductor layer between the pair of trenches.

A method of manufacturing a power semiconductor device according to another aspect of the present invention for solving the above problem is to form at least one trench to be recessed by a predetermined depth from the surface of the semiconductor layer into the semiconductor layer, and the at least one trench Defining a well region in the semiconductor layer on one side of the at least one trench, and defining a floating region in the semiconductor layer on the other side of the at least one trench; a portion formed on a sidewall of the at least one trench and adjacent to the floating region Forming a gate insulating layer including a sidewall portion having a thickness greater than that of a portion adjacent to the well region, and forming a gate electrode layer on the gate insulating layer to fill the at least one trench. .

According to the method of manufacturing the power semiconductor device, the forming of the gate insulating layer may include forming a lower buried portion filling a lower portion of the at least one trench, and forming the sidewall portion on the lower buried portion. It may include.

According to the method of manufacturing the power semiconductor device, a thickness of the lower buried portion may be formed to be thicker than a thickness of the sidewall portion.

According to the method of manufacturing the power semiconductor device, the semiconductor layer may be doped with an impurity of a first conductivity type, and the well region and the floating region may be doped with an impurity of a second conductivity type opposite to the first conductivity type. have.

According to the method of manufacturing the power semiconductor device, the forming of the at least one trench includes forming at least one pair of trenches extending in a stripe type, and the well region is between the pair of trenches. May be formed on the semiconductor layer.

According to the power semiconductor device and the method of manufacturing the same according to an embodiment of the present invention made as described above, it is possible to increase the reliability of the device by suppressing the negative gate charging (NGC) phenomenon.

Of course, these effects are exemplary, and the scope of the present invention is not limited by these effects.

1 is a schematic plan view showing a power semiconductor device according to an embodiment of the present invention.
2 is a circuit diagram showing a power semiconductor device according to an embodiment of the present invention.
3 is a circuit diagram showing a part of the power semiconductor device of FIG. 2.
4 is a cross-sectional view illustrating a power semiconductor device according to an embodiment of the present invention.
5 to 9 are cross-sectional views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention.
10 is a graph showing an operation wave form of a conventional power semiconductor device due to a negative gate charging (NGC) phenomenon.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and the following embodiments make the disclosure of the present invention complete, and the scope of the invention to those of ordinary skill in the art. It is provided to fully inform you. In addition, for convenience of description, in the drawings, at least some of the constituent elements may be exaggerated or reduced in size. In the drawings, the same reference numerals refer to the same elements.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for the sake of explanation, and thus are provided to describe the general structures of the present invention.

The same reference numerals denote the same elements. When referring to a configuration such as a layer, region, or substrate as being on another configuration, it will be understood that it is in the immediately upper trench of the other configuration or that there may also be other intervening configurations in between. On the other hand, when it is referred to as being "directly on" of another configuration, it is understood that there are no intervening configurations.

1 is a schematic plan view showing a power semiconductor device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a power semiconductor device according to an embodiment of the present invention, and FIG. 3 is It is a schematic diagram showing a part.

Referring to FIG. 1, the power semiconductor device 100 may be implemented using a semiconductor layer 105 including a main cell area MC and a sensor area SA. The power semiconductor device 100 may include a wafer, chip, or die structure.

A plurality of power semiconductor transistors (PT of FIG. 3) may be formed in the main cell area MC. A plurality of current sensor transistors (ST in FIG. 3) may be formed in the sensor area SA to monitor currents of the power semiconductor transistors PT.

For example, the two power semiconductor transistors PT and the current sensor transistors ST may include an insulated gate bipolar transistor (IGBT) or a power MOSFET structure. The IGBT may include a gate electrode, an emitter electrode, and a collector electrode. In FIGS. 2 to 3, an IGBT is described as an example as the power semiconductor device 100.

1 to 3, the power semiconductor device 100 may include a plurality of terminals for connection with the outside.

For example, the power semiconductor device 100 includes an emitter terminal 69 connected to the emitter electrodes of the power semiconductor transistors PT, and a Kelvin emitter connected to the Kelvin emitter electrodes of the power semiconductor transistors PT. The terminal 66, the current sensor terminal 64 connected to the emitter electrode of the current sensor transistors ST for monitoring current, the gate electrode of the power semiconductor transistors PT, and the current sensor transistors ST. The gate terminal 62 connected to the gate electrode, the temperature sensor terminals 67 and 68 connected to the temperature sensor TC for monitoring the temperature, and/or the power semiconductor transistors PT and the current sensor transistors ST ) May include a collector terminal 61 connected to the collector electrode.

In FIG. 2, the collector terminal 61 may be formed on the rear surface of the semiconductor layer 105 in FIG. 1, and the emitter terminal 69 in FIG. 2 may be formed on the mail cell area MC in FIG. 1.

The temperature sensor TC may include a junction diode connected to the temperature sensor terminals 67 and 68. The junction diode may include a junction structure between at least one n-type impurity region and at least one p-type impurity region, such as a P-N junction structure, a P-N-P junction structure, an N-P-N junction structure, and the like.

This structure exemplarily describes a structure in which the temperature sensor TC is embedded in the power semiconductor device 100, but the temperature sensor TC may be omitted in a modified example of this embodiment.

The power semiconductor transistor PT is connected between the emitter terminal 69 and the collector terminal 61, and the current sensor transistor ST is the power semiconductor transistor PT between the current sensor terminal 64 and the collector terminal 61. ) And partially connected in parallel. The gate electrode of the current sensor transistor ST and the gate electrode of the power semiconductor transistor PT are sharedly connected to the gate terminal 62 through a predetermined resistance.

The current sensor transistor ST has substantially the same structure as the power semiconductor transistor PT, but may be reduced to a predetermined ratio. Accordingly, the output current of the power semiconductor transistor PT can be indirectly monitored by monitoring the output current of the current sensor transistor ST.

4 is a cross-sectional view illustrating a power semiconductor device 100 according to an embodiment of the present invention.

Referring to FIG. 4, the semiconductor layer 105 may refer to one or a plurality of layers of semiconductor material, and, for example, may refer to a part of a semiconductor substrate and/or one or multiple epitaxial layers. May be. For example, the semiconductor layer 105 may include a drift region 107 and a well region 110.

Furthermore, the semiconductor layer 105 may further include an emitter region 112 in the well region 110. Here, the emitter region 112 may also be referred to as a source region.

The semiconductor layer 105 may further include a floating region 125 between the gate electrodes 120 and connected to the lower portion of the gate electrode 120. The floating region 125 may be formed deeper than the bottom of the gate electrode 120 and may be formed to connect two adjacent gate electrodes 120. The floating region 125 may be formed in the semiconductor layer 105 opposite the well region 110 between two adjacent power semiconductor transistors PT.

For example, the drift region 107 and the emitter region 112 may have a first conductivity type, and the well region 110 and the floating region 125 may have a second conductivity type. The first conductivity type and the second conductivity type have opposite conductivity types, but may be any one of n-type and p-type, respectively. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

The drift region 107 may be provided as an epitaxial layer of a first conductivity type, and the well region 110 may be doped with an impurity of a second conductivity type to the epitaxial layer or a second conductivity type epitaxial layer. Can be formed. The source region 112 may be formed by doping an impurity of the first conductivity type in the well region 110 or by additionally forming an epitaxial layer of the first conductivity type.

Further, when the power semiconductor device 100 is an IGBT, a collector region (not shown) may be provided under the drift region 107, and a collector electrode (not shown) may be provided under the collector region to be connected to the collector region. . For example, the collector region 128 may be provided as an epitaxial layer having a second conductivity type under the drift region 107.

At least one trench 116 may be formed by being recessed from the surface of the semiconductor layer 105 to the inside of the semiconductor layer 105 by a predetermined depth. For example, in FIG. 4, a pair of trenches 116 is illustrated as an example, and the number of trenches 116 may be appropriately selected according to the performance of the power semiconductor device 100, and Do not limit the scope.

The trenches 116 may be formed in a stripe type or a closed loop type. Further, the trenches 116 may be rounded at their corners, for example, the lower corners to suppress the concentration of the electric field.

For example, as shown in FIG. 4, at least one pair of trenches 116 is extended in a stripe type, and the well region 110 is formed in the semiconductor layer 105 between the pair of trenches 116. The floating region 125 may be formed in the semiconductor layer 105 opposite to the well region 110 with the trenches 116 therebetween. Furthermore, when there are a plurality of trenches 116, the well region 110 and the floating region 125 may be formed alternately.

The gate insulating layer 118 may be formed on the surface of at least one trench 116. For example, the gate insulating layer 118 is formed on the sidewall of the trench 116 and the thickness of the portion adjacent to the floating area 125 may include a sidewall portion 118b that is thicker than the thickness adjacent to the well area 110. I can.

The structure of the sidewall portion 118b may reduce the gate-collector capacitance Cgc to suppress a negative gate charging (NGC) phenomenon. In particular, since the gate insulating layer 118 in the direction of the well region 110 is related to the operating voltage, it is difficult to freely set the thickness, but by thickening the gate insulating layer 118 in the direction of the floating region 125, which is less related to channel formation, Displacement current through the floating region 125 can be suppressed.

Furthermore, the gate insulating layer 118 may further include a lower buried portion 118a filling the lower portion of the trench 116, and the sidewall portion 118b may be formed on the lower buried portion 118a. The thickness of the lower buried portion 118a may be thicker than the thickness of the sidewall portion 118b.

Like the sidewall portion 118b, the lower buried portion 118a may reduce the gate-collector capacitance Cgc to suppress a negative gate charging (NGC) phenomenon. The lower buried portion 118a has almost no relation to the formation of the channel and has a greater degree of freedom than the sidewall portion 118b in terms of its thickness, and thus can be sufficiently thickened.

The gate electrode 120 may be recessed into the semiconductor layer 105 to fill at least one trench 116 formed in the semiconductor layer 105 and formed on the gate insulating layer 118. Like the trench 116, the number of gate electrodes 120 may be appropriately selected according to the operating specifications of the power semiconductor device 100, and the scope of this embodiment is not limited.

The emitter electrode 145 may be formed on the emitter region 112. An insulating layer 130 may be interposed between the semiconductor layer 105 and the emitter electrode 145.

Although the above description has been described on the assumption that the power semiconductor device is an IGBT, it can be applied to a power MOSFET as it is. For example, in the power MOSFET, there is no collector region, and a drain electrode may be disposed instead of the collector electrode.

5 to 9 are cross-sectional views illustrating a method of manufacturing a power semiconductor device according to an embodiment of the present invention.

Referring to FIG. 5, at least one trench 116 is formed to be recessed by a predetermined depth from the surface of the semiconductor layer 105 into the semiconductor layer 105, and the semiconductor layer 105 on one side of the trench 116 The well region 110 may be defined, and the floating region 125 may be defined in the semiconductor layer 116 on the other side of the trench 116.

For example, in the trench 116, a photoresist pattern is formed on the semiconductor layer 105 in which the drift region 107, the well region 110, and the floating region 125 are formed using a photolithography technique. It may be formed by etching the semiconductor layer 105 using the pattern as an etch passivation layer.

6 to 7, a sidewall portion 118b formed on the sidewall of the trench 116 and having a thickness of a portion adjacent to the floating area 125 is greater than that of a portion adjacent to the well area 110. The included gate insulating layer 118 may be formed.

Furthermore, the step of forming the gate insulating layer 118 further includes forming a lower buried portion 118a filling the lower portion of the trench 116, and the sidewall portion 118b is formed on the lower buried portion 118a. Can be formed on.

For example, as shown in FIG. 6, a gate insulating layer 118 filling the trench 116 may be formed.

Subsequently, as shown in FIG. 7, an asymmetric additional trench 116a is formed in the gate insulating layer 118 to form a lower buried portion 118a and a sidewall portion 118b. The additional trench 116a may be formed closer to the well region 110 than the floating region 125, and may be formed above a predetermined thickness from the bottom surface of the trench 116 to define the lower buried portion 118a. have.

Referring to FIG. 8, a gate electrode layer 120 may be formed on the gate insulating layer 118 to fill the trench 116. More specifically, the gate electrode layer 120 may be formed on the gate insulating layer 118 to fill the additional trench 116a.

For example, the gate electrode layer 120 may be formed by patterning or planarizing after forming a conductive layer filling the additional trench 116a. The gate electrode layer 120 may include metal or doped polysilicon.

Referring to FIG. 9, an emitter region 112 may be formed, an insulating layer 130 may be formed, and an emitter electrode 145 may be formed.

For example, the emitter region 112 may be formed by implanting impurities of the first conductivity type into a part of the well region 110 in contact with the gate electrode layer 120.

For example, the emitter electrode 145 may be formed by patterning after forming a conductive layer.

According to the above-described manufacturing method, the thickness of the lower buried portion 118a of the gate insulating layer 118 is increased, and the sidewall portion 118b in the direction of the floating region 125 is formed at the sidewall portion 118b in the direction of the well region 110. By making it thicker than ), the shape of the negative gate charging (NGC) can be suppressed by reducing the gate-collector capacitance (Cgc).

The present invention has been described with reference to the embodiments shown in the drawings, but these are merely exemplary, and those of ordinary skill in the art will appreciate that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100: power semiconductor device
105: semiconductor layer
107: drift area
110: well area
112: emitter area
118: gate insulating layer
120: gate electrode layer
125: floating area

Claims (7)

A semiconductor layer;
At least one trench formed by being recessed from the surface of the semiconductor layer by a predetermined depth into the semiconductor layer;
A well region defined in the semiconductor layer at one side of the at least one trench;
A floating region defined in the semiconductor layer on the other side of the at least one trench;
A gate insulating layer formed on sidewalls of the at least one trench and including sidewall portions having a thickness of a portion adjacent to the floating area greater than a thickness of a portion adjacent to the well area; And
A gate electrode layer formed on the gate insulating layer to fill the at least one trench;
Containing,
Power semiconductor device. The method of claim 1,
The gate insulating layer further includes a lower buried portion filling a lower portion of the at least one trench,
The sidewall portion is formed on the lower buried portion,
Power semiconductor device. The method of claim 2,
The thickness of the lower buried portion is thicker than the thickness of the sidewall portion,
Power semiconductor device. The method of claim 1,
The semiconductor layer is doped with impurities of a first conductivity type,
The well region and the floating region are doped with impurities of a second conductivity type opposite to the first conductivity type,
Power semiconductor device. The method of claim 1,
The at least one trench includes at least a pair of trenches elongated in a stripe type,
The well region is formed in the semiconductor layer between the pair of trenches,
Power semiconductor device. At least one trench is formed to be recessed by a predetermined depth from the surface of the semiconductor layer into the semiconductor layer, thereby defining a well region in the semiconductor layer at one side of the at least one trench, and at the other side of the at least one trench. Defining a floating region in the semiconductor layer;
Forming a gate insulating layer formed on sidewalls of the at least one trench and including sidewall portions having a thickness of a portion adjacent to the floating region greater than a thickness of a portion adjacent to the well region; And
Forming a gate electrode layer on the gate insulating layer to fill the at least one trench;
Containing,
A method of manufacturing a power semiconductor device. The method of claim 6,
Forming the gate insulating layer,
Forming a lower buried portion filling a lower portion of the at least one trench; And
Including the step of forming the sidewall portion on the lower buried portion,
A method of manufacturing a power semiconductor device.

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