KR102300623B1 - Power semiconductor device and power semiconductor chip - Google Patents

Abstract

A power semiconductor device according to one aspect of the present invention includes: a semiconductor layer; at least one trench including an upper trench formed by being recessed by a predetermined depth into the semiconductor layer from a surface of the semiconductor layer, and having a first width, and a lower trench formed in communication with the upper trench and having a second width smaller than the first width; a well region defined in the semiconductor layer on one side of the at least one trench; a floating region defined in the semiconductor layer on the other side of the at least one trench; a gate insulating layer formed on an inner wall of the at least one trench; and a gate electrode layer formed on the gate insulating layer to fill the at least one trench.

Description

Power semiconductor device and power semiconductor chip

The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device and a power semiconductor chip for switching power transmission.

A power semiconductor device is a semiconductor device that operates in a high voltage and high current environment. Such a power semiconductor device is used in a field requiring high power switching, for example, an inverter device. For example, the power semiconductor device may include an insulated gate bipolar transistor (IGBT), a power MOSFET, and the like. Such a power semiconductor device is fundamentally required to withstand high voltage, and recently, a high-speed switching operation is additionally required.

Such a semiconductor device operates while electrons injected from a channel and holes injected from a collector flow. However, in a trench gate type power semiconductor device, when holes are excessively accumulated in the trench gate, a negative gate charging (NGC) phenomenon occurs and a displacement current is generated in the gate direction.

Such a trench gate type power semiconductor device has a large gate-collector capacitance (Cgc), and thus is greatly affected by the negative gate charging (NGC), causing an issue in switching stability. Furthermore, as the gain of the bipolar junction transistor increases in such a power semiconductor device, the negative gate charging effect increases.

Republic of Korea Publication No. 20140057630 (published on May 13, 2014)

An object of the present invention is to provide a power semiconductor device and a power semiconductor chip capable of improving switching stability by suppressing a negative gate charging phenomenon.

However, these problems are exemplary, and the scope of the present invention is not limited thereto.

A power semiconductor device according to an aspect of the present invention for solving the above problems is formed by recessing a semiconductor layer by a predetermined depth from the surface of the semiconductor layer into the semiconductor layer, an upper trench having a first width and at least one trench formed in communication with the upper trench and including a lower trench having a second width smaller than the first width; a well region defined in the semiconductor layer at one side of the at least one trench; a floating region defined in the semiconductor layer on the other side of one trench; a gate insulating layer formed on an inner wall of the at least one trench; and a gate electrode layer formed on the gate insulating layer to fill the at least one trench. .

According to the power semiconductor device, the upper trench may be formed to protrude toward the side where the well region is located compared to the lower trench.

According to the power semiconductor device, the at least one trench may further include an intermediate trench, the width of which varies from the first width to the second width between the upper trench and the lower trench.

According to the power semiconductor device, the outer peripheral surface of the upper trench may be on the same line as the outer peripheral surface of the lower trench on the other side of the floating region.

According to the power semiconductor device, the well region may be formed to surround the one side of the upper trench and not to surround the lower trench.

According to the power semiconductor device, the floating region may be formed to surround the other side of the upper trench and the other side of the lower trench.

According to the power semiconductor device, a doping concentration of an upper portion in the upper trench of the gate electrode layer may be higher than a doping concentration of a lower portion in the lower trench of the gate electrode layer.

According to the power semiconductor device, the semiconductor layer is doped with an impurity of a first conductivity type,

The well region and the floating region may be doped with impurities of a second conductivity type opposite to the first conductivity type.

A power semiconductor chip according to another aspect of the present invention for solving the above problems, a semiconductor layer including a main cell region and a sensor region, is formed in the main cell region, and includes a plurality of power semiconductor devices described above power semiconductor transistors; a plurality of current sensor transistors formed in the sensor region to monitor currents of the power semiconductor transistors; an emitter terminal connected to an emitter electrode of the plurality of power semiconductor transistors; a current sensor terminal connected to the emitter electrode of the current sensor transistors of

According to the power semiconductor device and the power semiconductor chip according to the embodiment of the present invention made as described above, it is possible to suppress the negative gate charging (NGC) phenomenon to increase the switching stability.

Of course, these effects are exemplary, and the scope of the present invention is not limited by these effects.

1 is a schematic plan view showing a power semiconductor chip according to an embodiment of the present invention.
2 is a circuit diagram illustrating a power semiconductor chip according to an embodiment of the present invention.
3 is a circuit diagram illustrating a part of the power semiconductor chip of FIG. 2 .
4 is a cross-sectional view showing a power semiconductor device according to an embodiment of the present invention.
5 is a graph showing voltage-current characteristics of power semiconductor devices according to Examples and Comparative Examples of the present invention.
6 is a graph showing the strength of the electric field according to the depth of the power semiconductor devices according to the embodiments of the present invention and the comparative example.
7 is a graph showing voltage and current characteristics according to time of power semiconductor devices according to Examples and Comparative Examples of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. It is provided to fully inform In addition, in the drawings for convenience of description, the size of at least some of the components may be exaggerated or reduced. In the drawings, like reference numerals refer to like elements.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In the drawings, the sizes of layers and regions are exaggerated for the sake of illustration, and are therefore provided to illustrate the general structures of the present invention.

Like reference signs indicate like elements. It will be understood that when referring to one configuration as being on another configuration, such as a layer, region, or substrate, it may also be in a trench immediately above the other configuration or other intervening configurations in between. On the other hand, when referring to one configuration as being “directly on” of another, it is understood that intervening configurations do not exist.

1 is a schematic plan view showing a power semiconductor chip 50 according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a power semiconductor chip 50 according to an embodiment of the present invention, and FIG. 3 is FIG. It is a circuit diagram showing a part of the power semiconductor chip of

Referring to FIG. 1 , a power semiconductor chip 50 may be formed using a semiconductor layer 105 including a main cell area MC and a sensor area SA. The power semiconductor chip 50 may include a wafer die or a packaging structure.

A plurality of power semiconductor transistors (PT of FIG. 3 ) may be formed in the main cell region MC. A plurality of current sensor transistors (ST of FIG. 3 ) may be formed in the sensor area SA to monitor currents of the power semiconductor transistors PT.

For example, the power semiconductor transistors PT and the current sensor transistors ST may include an insulated gate bipolar transistor (IGBT) structure or a power MOSFET structure. The IGBT may include a gate electrode, an emitter electrode, and a collector electrode. In FIGS. 2 to 3 , a case in which the power semiconductor transistors PT and the current sensor transistors ST are IGBTs will be described as an example.

1 to 3 , the power semiconductor chip 50 may include a plurality of terminals for connection to the outside.

For example, the power semiconductor chip 50 includes an emitter terminal 69 connected to the emitter electrode of the power semiconductor transistors PT, and a Kelvin emitter connected to the Kelvin emitter electrode of the power semiconductor transistors PT. terminal 66, a current sensor terminal 64 connected with an emitter electrode of the current sensor transistors ST for monitoring a current, a gate electrode of the power semiconductor transistors PT, and the current sensor transistors ST. The gate terminal 62 connected to the gate electrode, the temperature sensor terminals 67 and 68 connected to the temperature sensor TC for monitoring the temperature and/or the power semiconductor transistors PT and the current sensor transistors ST ) may include a collector terminal 61 connected to the collector electrode.

In FIG. 2 , the collector terminal 61 may be formed on the rear surface of the semiconductor layer 105 of FIG. 1 , and in FIG. 2 , the emitter terminal 69 may be formed on the mail cell region MC of FIG. 1 .

The temperature sensor TC may include a junction diode connected to the temperature sensor terminals 67 and 68 . The junction diode may include a junction structure of at least one n-type impurity region and at least one p-type impurity region, for example, a P-N junction structure, a P-N-P junction structure, an N-P-N junction structure, or the like.

Although this structure exemplarily describes a structure in which the temperature sensor TC is built in the power semiconductor chip 50 , the temperature sensor TC may be omitted in a modified example of this embodiment.

The power semiconductor transistor PT is connected between the emitter terminal 69 and the collector terminal 61 , and the current sensor transistor ST is connected between the current sensor terminal 64 and the collector terminal 61 , the power semiconductor transistor PT ) and some parallel connections. The gate electrode of the current sensor transistor ST and the gate electrode of the power semiconductor transistor PT are commonly connected to the gate terminal 62 via a predetermined resistor.

The current sensor transistor ST has a structure substantially the same as that of the power semiconductor transistor PT, but may be reduced by a predetermined ratio. Accordingly, the output current of the power semiconductor transistor PT may be indirectly monitored by monitoring the output current of the current sensor transistor ST.

For example, the power semiconductor transistor PT and/or the current sensor transistor ST may include the structure of the power semiconductor device 100 of FIG. 4 . In some embodiments, the power semiconductor transistor PT and the power semiconductor device 100 may be used interchangeably.

4 is a cross-sectional view showing the power semiconductor device 100 according to an embodiment of the present invention.

Referring to FIG. 4 , semiconductor layer 105 may refer to one or more semiconductor material layers, for example, a portion of a semiconductor substrate and/or one or multiple epitaxial layers. may be

The at least one trench 116 may be formed by recessing a predetermined depth into the semiconductor layer 105 from the surface of the semiconductor layer 105 . For example, in FIG. 4 , a pair of trenches 116 is exemplarily shown, and the number of trenches 116 may be appropriately selected according to the performance of the power semiconductor device 100 , and in this embodiment does not limit the scope.

The trenches 116 may be formed in a stripe type, a closed loop type, or a ladder type. Furthermore, the trenches 116 may have their edges, for example, bottom edges, rounded to suppress the concentration of the electric field.

The trench 116 may include an upper trench 116a having a first width W1 and a lower trench 116b having a second width W2 . For example, the lower trench 116b may be formed below the upper trench 116a to communicate with the upper trench 116a, and the second width W2 may be smaller than the first width W1 .

Further, the trench 116 may further include an intermediate trench 116c between the upper trench 116a and the lower trench 116b. The width of the middle trench 116c may vary from the first width W1 to the second width W2 in order to connect the upper trench 116a and the lower trench 116b to each other.

For example, the semiconductor layer 105 may include a drift region 107 and a well region 110 . Furthermore, the semiconductor layer 105 may further include an emitter region 112 in the well region 110 . Here, the emitter region 112 may be referred to as a source region. Furthermore, the semiconductor layer 105 may further include a floating region 125 .

More specifically, the well region 110 may be limited to the semiconductor layer 105 at one side of the trench 116 . The floating region 125 may be defined in the semiconductor layer 105 on the other side of the trench 116 . Furthermore, the floating region 125 may further extend to a lower portion of the trench 116 for electric field relaxation. For example, the well region 110 and the floating region 125 may be doped with the same type.

For example, when the trenches 116 are formed in a closed loop type or a ladder type, the well region 110 is defined in the semiconductor layer 105 surrounded by the trenches 116 , and the floating region 125 is the trench. It may be limited to the semiconductor layer 105 located outside the poles 116 .

As another example, when the trenches 116 are formed in a stripe type, the well region 110 and the floating region 125 may be alternately formed between the trenches 116 .

The emitter region 112 may be formed adjacent to the trenches 116 to a predetermined depth in the well region 110 . The emitter region 112 and the well region 110 may be doped in opposite types.

The drift region 107 is defined between the trenches 116 in contact with the well region 110 , and may further extend below the floating region 125 and the lower surface of the semiconductor layer 105 .

For example, the drift region 107 and the emitter region 112 may have a first conductivity type, and the well region 110 and the floating region 125 may have a second conductivity type. The first conductivity type and the second conductivity type have opposite conductivity types, but may be either n-type or p-type, respectively. For example, if the first conductivity type is n-type, the second conductivity type is p-type, and vice versa.

In some embodiments, the drift region 107 may be provided as an epitaxial layer of a first conductivity type, and the well region 110 may be doped with an impurity of a second conductivity type in this epitaxial layer or a second conductivity type. It can be formed as an epitaxial layer of The emitter region 112 may be formed by doping an impurity of the first conductivity type in the well region 110 or by additionally forming an epitaxial layer of the first conductivity type.

In this embodiment, the structure of the trench 116 may be formed such that the upper trench 116a protrudes to one side where the well region 110 is located compared to the lower trench 116b in order to suppress negative gate charging (NGC). have. On the other hand, the outer peripheral surface of the upper trench 116a may be on the same line as the lower trench 116b at the other side of the trench 116 having the floating region 125 . Accordingly, the trench 116 may have an asymmetric shape in which the upper trench 116a protrudes toward the well region 110 as a whole.

Meanwhile, in FIG. 4 , the intermediate trench 116b is illustrated as having a recessed notch structure in a portion adjacent to the floating region 125 , but may be formed in a straight line without a notch in a modified example of this embodiment.

Furthermore, the well region 110 may be formed to surround one side of the upper trench 116a but not to surround the lower trench 116b. That is, the bottom surface of the well region 110 may be located near the bottom of the upper trench 116a or the middle trench 116 .

The floating region 125 may be formed to surround the other side of the upper trench 116a and the other side of the lower trench 116b. Further, the floating region 125 is formed deeper than the lower trench 116b to further surround the lower surface of the lower trench 116b while surrounding the upper trench 116a, the middle trench 116b, and the other side of the lower trench 116b. can be

Furthermore, when the power semiconductor device 100 is an IGBT, a collector region (not shown) may be provided under the drift region 107, and a collector electrode (not shown) may be provided under the collector region to be connected to the collector region. . For example, the collector region 128 may be provided under the drift region 107 as an epitaxial layer having a second conductivity type different from that of the drift region 107 .

As another example, when the power semiconductor device 100 is a power MOSFET, a drain electrode may be connected under the drift region 107 .

The gate insulating layer 118 may be formed on an inner wall of the at least one trench 116 . For example, the gate insulating layer 118 may be formed on the inner wall of the trench 116 to have a uniform thickness over the upper trench 116a , the middle trench 116c , and the lower trench 116b .

The gate electrode layer 120 may be formed on the gate insulating layer 118 to fill the at least one trench 116 . For example, the gate electrode layer 120 may be formed to be recessed into the semiconductor layer 105 , and in this sense, it may be understood to have a recess type or a trench type.

The arrangement of the gate electrode layer 120 on a plane may follow the arrangement shape of the trench 116 , and thus may have a closed loop type, a ladder type, or a stripe type. The number of the gate electrode layers 120 may be appropriately selected according to the operating specifications of the power semiconductor device 100 , like the trenches 116 , and the scope of this embodiment is not limited.

The shape of the gate electrode layer 120 in the trench 116 may correspond to the structure of the trench 116 . Accordingly, the upper portion of the gate electrode layer 120 may be formed to protrude to one side where the well region 110 is located, compared to the lower portion. On the other hand, the gate electrode layer 120 on the other side of the trench 116 may be on the same line. Accordingly, the gate electrode layer 120 may have an asymmetric shape in which an upper portion protrudes toward the well region 110 as a whole.

The emitter electrode 145 may be formed on the emitter region 112 . The emitter electrode 145 may be commonly connected to the emitter region 112 and the well region 110 . An insulating layer 130 may be interposed between the semiconductor layer 105 and the emitter electrode 145 .

According to the structure of the trench 116 and the gate electrode layer 120 , when the power semiconductor device 100 is operated, the upper trench 116a protrudes so that the channel in the well region 110 is spaced apart from the lower trench 116b. According to the arrangement, a movement path of a hole may be partially spaced apart from the lower trench 116b. Accordingly, when the power semiconductor device 100 is operated, the distribution of the electric field may also be formed in a direction away from the lower trench 116b.

Accordingly, according to this structure, the gate-collector capacitance (Cgc) in the static state and the gate-collector capacitance (Cgc) in the dynamic state may vary.

Accordingly, when the power semiconductor device 100 is operated, when the hole flows into the emitter region 112 , the hole movement path is partially spaced from the lower trench 116b so that the gate-collector capacitance Cgc in a dynamic state ) to reduce the negative gate charging (NGC) phenomenon.

In some embodiments, the negative gate charging (NGC) phenomenon may be further controlled by adjusting the doping concentration of the gate electrode layer 120 . For example, by making the doping concentration of the upper portion in the upper trench 116a of the gate electrode layer 120 higher than the doping concentration of the lower portion in the lower trench 116b of the gate electrode layer 120 , The negative gate charging (NGC) phenomenon may be reduced by adjusting the electric field.

Although the above descriptions have been made on the assumption that the power semiconductor device is an IGBT, it may be applied to a power MOSFET as it is.

Hereinafter, the characteristics of the power semiconductor devices according to the embodiments of the present invention and the comparative example will be compared and described. Hereinafter, Embodiment 1 refers to the power semiconductor device 100 having the structure of FIG. 4 , and Embodiment 2 refers to the upper portion in the upper trench 116a of the gate electrode layer 120 in the power semiconductor device 100 of FIG. 4 . It refers to a case in which the doping concentration of the portion is higher than the doping concentration of the lower portion in the lower trench 116b of the gate electrode layer 120, and in the comparative example, the trench and the gate electrode layer have a uniform width without upper and lower divisions, unlike the embodiments. case is formed.

5 is a graph showing voltage-current characteristics of power semiconductor devices according to Examples and Comparative Examples of the present invention.

Referring to FIG. 5 , from the collector-emitter current (Ice) graph according to the collector-emitter voltage (Vce), in Examples 1 and 2 compared to Comparative Examples, carrier movement is relatively free. It can be seen that the resistance decreases. In particular, it can be seen that the improvement effect is greater when the current is large due to the large amount of carriers.

Furthermore, in the case of Example 2 compared to Example 1, it can be seen that the effect is larger. From this, it can be seen that adjusting the doping concentration of the gate electrode layer 120 in addition to the shape of the trench 116 and the gate electrode layer 120 is more effective in improving the current characteristics.

6 is a graph showing the strength of the electric field according to the depth of the power semiconductor devices according to the embodiments of the present invention and the comparative example. In FIG. 6 , the first depth D1 represents a depth of the bottom surface of the well region 110 in the power semiconductor device 100 , and the second depth D2 is approximately the floating region 125 in the power semiconductor device 100 . ) represents the depth of the bottom surface.

Referring to FIG. 6 , it can be seen that the electric field strength at the first depth D1 is lowered in Examples 1 and 2 compared to Comparative Examples. An electric field strength at the first depth D1 may indicate a peak electric field strength of a junction field effect transistor (JFET) region of the power semiconductor device 100 .

Therefore, it can be seen that in Examples 1 and 2, a margin for improving resistance can be additionally secured by lowering the intensity of the peak electric field compared to Comparative Examples. That is, by securing an additional margin of the junction between the well region 110 and the drift region 107 , it is possible to secure a resistance improvement margin according to an increase in the doping concentration of the drift region 107 .

7 is a graph showing voltage and current characteristics according to time of power semiconductor devices according to Examples and Comparative Examples of the present invention.

Referring to FIG. 7 , in the switching simulation, in the case of Examples 1 and 2, it can be seen that the Miller period is reduced compared to the Comparative Example. Accordingly, in the case of Examples 1 and 2, it can be seen that the turn-on and turn-off are faster, and the loss is reduced because the carrier annihilation is fast compared to the Comparative Example.

Therefore, it can be seen that in the case of Examples 1 and 2, switching stability can be improved compared to Comparative Examples.

1 to 3 , the power semiconductor chip 50 may use the power semiconductor device 100 of FIG. 4 as a power semiconductor transistor (PT) and/or a current sensor transistor (ST), and thus the power semiconductor device ( The features of 100 can be applied to the power semiconductor chip 50 as it is.

In the power semiconductor device 100 and the power semiconductor chip 50 using the power semiconductor device 100, by changing the shape of the trench 116 and the gate electrode layer 120, the negative gate charging phenomenon is suppressed, It can be seen that the switching stability can be improved. Furthermore, it can be seen that the resistance characteristic can be further improved by adjusting the doping concentration of the gate electrode layer 120 .

Although the present invention has been described with reference to the embodiments shown in the drawings, which are merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

50: power semiconductor chip
100: power semiconductor device
105: semiconductor layer
107: drift zone
110: well area
112: emitter area
118: gate insulating layer
120: gate electrode layer
125: floating area
130: insulating layer
145: emitter electrode

Claims (9)

semiconductor layer;
An upper trench formed by recessing a predetermined depth into the semiconductor layer from the surface of the semiconductor layer, an upper trench having a first width, and a lower trench formed in communication with the upper trench and having a second width smaller than the first width at least one trench comprising;
a well region defined in the semiconductor layer at one side of the at least one trench;
a floating region defined in the semiconductor layer on the other side of the at least one trench;
a gate insulating layer formed on an inner wall of the at least one trench; and
a gate electrode layer formed on the gate insulating layer to fill the at least one trench;
including,
The upper trench is formed to protrude to the side where the well region is located compared to the lower trench,
The outer circumferential surface of the upper trench is on the same line as the outer circumferential surface of the lower trench at the other side where the floating region is,
power semiconductor devices. delete The method of claim 1,
wherein the at least one trench further comprises an intermediate trench varying in width from the first width to the second width between the upper trench and the lower trench.
power semiconductor devices. delete The method of claim 1,
The well region is formed to surround the one side of the upper trench and not to surround the lower trench,
power semiconductor devices. 6. The method of claim 5,
The floating region is formed to surround the other side of the upper trench and the other side of the lower trench,
power semiconductor devices. The method of claim 1,
a doping concentration of an upper portion in the upper trench of the gate electrode layer is higher than a doping concentration of a lower portion in the lower trench of the gate electrode layer;
power semiconductor devices. The method of claim 1,
The semiconductor layer is doped with an impurity of a first conductivity type,
the well region and the floating region are doped with an impurity of a second conductivity type opposite to the first conductivity type;
power semiconductor devices. a semiconductor layer including a main cell region and a sensor region;
A plurality of power semiconductor transistors formed in the main cell region, comprising the power semiconductor device according to any one of claims 1, 3 and 5 to 8;
a plurality of current sensor transistors formed in the sensor region to monitor currents of the power semiconductor transistors;
an emitter terminal connected to the emitter electrodes of the plurality of power semiconductor transistors;
a current sensor terminal connected to an emitter electrode of the plurality of current sensor transistors; and
a gate terminal connected to a gate electrode of the power semiconductor transistors and a gate electrode of the plurality of current sensor transistors;
power semiconductor chip.

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