KR20190093488A - Semiconductor package - Google Patents

Abstract

Present a semiconductor package. The package substrate of the semiconductor package includes a plurality of second conductive lines arranged on the first surface of the base layer and electrically connected to the first conductive lines of the first layer on the second surface. Place them. A plating lead line is connected to one of the conductive lines of the first layer, and a provisional bridge line electrically connects the conductive lines of the second layer to each other. The dielectric layer provides an opening hole that breaks the middle portion of the temporary bridge line and separates it into first and second residual portions. The first conductive line of the conductive lines of the second layer is connected to the first residual portion, and the second conductive line of the conductive lines of the second layer is connected to the second residual portion. The first and second conductive lines are conductive lines to which operating voltages of substantially the same potential are applied.

Description

Semiconductor Package {Semiconductor package}

The present application relates to a semiconductor package.

The semiconductor package includes a package substrate on which a semiconductor chip is mounted. The package substrate includes a circuit wiring structure electrically connected to a semiconductor chip. A plating layer is formed on a part of the circuit wiring. The plating layer may increase the adhesion between the circuit wiring and the connector connected thereto, and may improve the electrically conductivity.

The present application proposes a semiconductor package structure with reduced plating lines for electrolytic plating.

One aspect of the present application, a semiconductor chip; And a package substrate on which the semiconductor chip is mounted. A base layer including first and second surfaces opposite to each other; A first bonding finger disposed on the first surface of the base layer; A plating lead line spaced apart from the first bonding finger on the first surface of the base layer; A first conductive via electrically connected to the first bonding finger and substantially passing through the base layer; A second conductive via electrically connected to the plating inlet line and spaced apart from the first conductive via; First and second ball lands respectively connected to the first and second conductive vias at a second surface of the base layer; A first provisional bridge line electrically connecting the first conductive via to the second conductive via at a second surface of the base layer; And a dielectric layer covering a second surface of the base layer, the dielectric layer providing an opening hole that breaks an intermediate portion of the first temporary bridge line and separates the first and second residual portions spaced apart from each other. Present the substrate. The first ball land electrically connected to the first residual portion and the second ball land connected to the second residual portion may be ball lands to which operating voltages of substantially the same potential are applied.

One aspect of the present application, a semiconductor chip; And a package substrate on which the semiconductor chip is mounted. A base layer including first and second surfaces opposite to each other; Conductive lines of a plurality of first layers disposed on the first surface of the base layer; A plurality of second conductive lines disposed on a second surface of the base layer and electrically connected to the conductive lines of the first layer, respectively; A plating lead line connected to a first conductive line of the conductive lines of the first layer; A provisional bridge line electrically connecting the conductive lines of the second layer to each other; And a dielectric layer covering a second surface of the base layer, the dielectric layer providing an opening hole that breaks an intermediate portion of the temporary bridge line and separates the first and second remaining portions spaced apart from each other. To present. Among the conductive lines of the second layer, the second conductive line connected to the first residual portion and the third conductive line connected to the second residual portion may be conductive lines to which operating voltages of substantially the same potential are applied. .

One aspect of the present application, a semiconductor chip; And a package substrate on which the semiconductor chip is mounted. A base layer including first and second surfaces opposite to each other; A plurality of first group of conductive lines and a second group of conductive lines disposed on the first surface of the base layer; A plurality of third and fourth groups of conductive lines disposed on a second surface of the base layer and electrically connected to the first and second groups of conductive lines, respectively; A first plating lead line connected to a first conductive line of one of the first group of conductive lines; A second plating lead line connected to one second conductive line of the second group of conductive lines; Provisional bridge lines of a first group electrically connecting the conductive lines of the third group to each other; Temporary bridge lines of a second group electrically connecting the conductive lines of the fourth group to each other; And a first opening hole covering the second surface of the base layer and separating the middle portion of the temporary bridge line of the first group to separate the first and second residual portions spaced apart from each other, and the first opening hole. A package substrate is provided that includes a dielectric layer that provides a second opening hole that breaks the middle portion of the two groups of temporary bridge lines and separates them into third and fourth residual portions spaced apart from each other. The first and second residual portions are conductive lines to which operating voltages of the same first potential are applied, and the third and fourth residual portions are equally applied to operating voltages of the second potential different from the first potential. May be conductive lines.

According to embodiments of the present application, a semiconductor package structure including a package substrate having reduced plating lines may be provided. The number of plating lines in the package substrate may be reduced. The overall length of the plating lines in the package substrate may be shortened. Accordingly, the plating lines can effectively suppress the unwanted action of deteriorating the operating characteristics of the semiconductor package or degrading signal integrity. The structure of the package substrate can suppress or prevent the occurrence of electro-chemical migration defects.

1 is a cross-sectional view illustrating a semiconductor package according to an embodiment.
2 is a cross-sectional view schematically illustrating a cross-sectional structure of a package substrate before opening holes are formed, according to an exemplary embodiment.
FIG. 3 is a plan view schematically illustrating a top circuit layout of the package substrate of FIG. 2.
FIG. 4 is a plan view schematically illustrating a bottom circuit layout of the bottom surface of the package substrate of FIG. 2.
5 is a cross-sectional view schematically illustrating a cross-sectional structure of a package substrate with opening holes according to an exemplary embodiment.
6 to 9 are plan views schematically illustrating a package substrate having opening holes, according to an exemplary embodiment.
10 is a cross-sectional view illustrating a semiconductor package according to an embodiment.
FIG. 11 illustrates an example in which electro-chemical migration (ECM) defects are generated in a semiconductor package.
12 is a plan view illustrating a top circuit wiring layout of a package substrate according to an exemplary embodiment.
13 is a plan view illustrating a top circuit wiring layout of a package substrate according to a comparative example.

Terms used in the description of the examples of the present application are terms selected in consideration of functions in the exemplary embodiments, and the meaning of the terms may vary according to the intention or custom of the user or operator in the technical field. Meaning of the terms used are defined according to the definition defined when specifically defined herein, and may be interpreted as meaning generally recognized by those skilled in the art in the absence of a specific definition. In the description of the examples of the present application, descriptions such as "first" and "second", "top" and "bottom or lower" are intended to distinguish the members, and define the members themselves or in a specific order. It is not meant to be used.

The semiconductor package may include electronic devices such as a semiconductor die or a semiconductor chip, and the semiconductor die or chip may include a form in which a semiconductor substrate in which an electronic circuit is integrated is cut into dies or chips. A semiconductor chip is a memory chip in which memory integrated circuits such as DRAM, SRAM, NAND FLASH, NOR FLASH, MRAM, ReRAM, FeRAM, or PcRAM are integrated, or logic or logic logic integrated in a semiconductor substrate. It can mean an ASIC chip. The semiconductor package may be applied to an information communication device such as a portable terminal, bio or health care related electronic devices, or wearable electronic devices.

Like reference numerals refer to like elements throughout the specification. The same or similar reference numerals may be described with reference to other drawings even if they are not mentioned or described in the corresponding drawings. Also, although reference numerals are not indicated, they may be described with reference to other drawings.

In a semiconductor package, a semiconductor chip is mounted on a package substrate. The package substrate includes a circuit wiring structure electrically connected to a semiconductor chip. A plating layer is formed on a part of the circuit wiring. The plating layer may increase the adhesion between the circuit wiring and the connector connected thereto, and may improve the electrically conductivity.

The plating layer may be formed by an electrolytic plating method. Plating lines are connected to the circuit wiring to apply the electroplating process. Plating lines are introduced into elongated conductive patterns connected to circuit wiring, for example signal lines, from the edge of the package substrate. The plating lines are conductive lines necessary for electrolytic plating, but they do not function as circuit wirings required for the operation of the semiconductor package.

In the process of operating the semiconductor package, the plating lines may serve as unnecessary transmission lines such as stubs. The plating lines connected to the signal lines may serve as a path through which the signal is bypassed or as a path through which the signal is reflected. As the signal is unnecessarily reflected along the plating lines, the signal transmission speed may be undesirably degraded, an operation characteristic of the semiconductor package may be degraded, or signal integrity may be degraded. The present application proposes a semiconductor package structure including a package substrate which reduces and shortens the overall length of the plating lines.

External environmental changes, such as changes in humidity or temperature, can cause electro-chemical migration (ECM) defects in the package substrate. The present application proposes a semiconductor package employing a package substrate structure capable of suppressing or preventing electrochemical transfer (ECM) defects.

1 is a cross-sectional view schematically showing a cross-sectional structure of a semiconductor package 10 according to an embodiment. 2 is a cross-sectional view schematically showing a cross-sectional structure of a package substrate 100 according to one embodiment. The package substrate 100 of FIG. 2 shows a form before the opening holes 117 of the package substrate 100F of FIG. 1 are formed. FIG. 3 is a plan view schematically illustrating a top circuit layout 101 of the package substrate 100 of FIG. 2. FIG. 4 is a plan view schematically illustrating a bottom circuit layout 102 of the package substrate of FIG. 2.

Referring to FIG. 1, the semiconductor package 10 includes a semiconductor chip 130 mounted on a package substrate 100F. The package substrate 100F includes first and second residual portions 122A and 122B of the plating lead line 121 and the provisional bridge line for plating 126. The opening hole 117 breaks the middle portion of the temporary bridge line 126 so that the first and second residual portions 122A and 122B of the temporary bridge line face each other. The first and second remaining portions 122A and 122B of the temporary bridge line are connected to wires to which operating voltages of the same potential are applied, respectively.

The semiconductor chip 130 is mounted on the first dielectric layer 115 of the package substrate 100F. A molding layer 139 covering the semiconductor chip 130 is formed on the first dielectric layer 115 of the package substrate 100F. A bonding wire 135 electrically connects a bonding finger 140 to a contact pad 131 of the semiconductor chip 130. The bonding wire 135 is connected to the bonding finger 140 through the first plating layer 151. Solder ball 136 may be coupled to the second plating layer 152 as an outer connector.

Referring to FIG. 2, the package substrate 100 shows a pre-packaging substrate in a form before the opening hole 117 of the package substrate 100F of FIG. 1 is formed. The package substrate 100 includes a base layer 110, and a plating line structure is provided on the base layer 110. The base layer 110 may be a layer of dielectric material forming a body or core of the package substrate 100. The plating line structure includes a lead line for plating 121 and temporary bridge lines 126. Temporary bridge line 126 includes a first temporary bridge line 122. As shown in FIG. 3, the temporary bridge line 126 may further include second to fourth temporary bridge lines 123, 124, and 125.

The base layer 110 has a first surface 111 and a second surface 112, which are surfaces opposite to each other. The first dielectric layer 115 is formed on the first surface 111 of the base layer 110, and the second dielectric layer 116 is formed to cover the second surface 112. The first dielectric layer 115 or the second dielectric layer 116 may be formed of a layer including a solder resist layer. The package substrate 100 may be provided in a printed circuit board (PCB) structure. The package substrate 100 may be provided in a ball grid array (BGA) substrate structure.

The package substrate 100 may include a boundary region 104 and an inner region 103 positioned inside the boundary region 104. The boundary region 104 is a region surrounding the inner region 103 of the package substrate 100. The package substrate 100 is introduced in a form in which another inner region 103 ′ adjacent to the inner region 103 is connected by the boundary region 104.

The inner region 103 of the package substrate 100 is a region where the semiconductor chip 130 is mounted in the region. The inner region 103 may be a region where circuit wirings electrically connected to the semiconductor chip 130 are located. The semiconductor chip 130 is mounted in the inner region 103. The semiconductor chip 130 is mounted above the first surface 111 of the base layer 110. The semiconductor chip 130 may be attached on the first dielectric layer 115. The boundary region 104 may be a region removed in the final process of packaging the semiconductor chip 130. The boundary region 104 may be a region that is removed in a sawing process of molding the semiconductor chip 130 mounted on the package substrate 100 and then separating the semiconductor chips 130 into individual semiconductor packages.

Referring to FIG. 3, upper circuit wiring lines are provided on the first surface 111 of the base layer 110 of the package substrate 100. As depicted in the layout 101 of the top circuit wirings, the top circuit wirings are bonding fingers 140, trace pattern of first layer 160 and plating lead line 121. ).

The bonding fingers 140 are spaced apart from each other and disposed on the first surface 111 of the base layer 110. For example, the second bonding finger 142, the third bonding finger 143, and the fourth bonding finger 144 are disposed to be spaced apart from the first bonding finger 141. The bonding fingers 140 may be disposed around the semiconductor chip 130 for electrical connection with the semiconductor chip 130.

The first bonding fingers 141 and the third and fourth bonding fingers 143 and 144 of the bonding fingers 140 constitute signal lines for applying a signal to the semiconductor chip 130. Provide some parts. Signal lines are conductive paths to which data signals (DQ signals) or address and command signals are applied. Signals are applied to the semiconductor chip 130 through the first bonding finger 141 and the third and fourth bonding fingers 143 and 144. On the other hand, the second bonding finger 142 is a part of the power line for applying power to the semiconductor chip 130.

Trace patterns 160 of the first layer are conductive lines extending from the bonding fingers 140. Trace patterns 160 of the first layer electrically connect the bonding fingers 140 to each of the conductive vias 180. The trace patterns 160 of the first layer may include first to fourth trace patterns 161, 162, 163, and 164.

4 and 2, bottom circuit lines are provided on the second surface 112 of the base layer 110 of the package substrate 100. As depicted in the layout 102 of the bottom circuit wirings, the bottom circuit wirings may include ball lands 190, trace patterns 170 of the second layer and a plurality of temporary bridge lines 126. Include. Trace patterns 170 of the second layer are disposed on the second surface 112 of the base layer 110.

Each of the conductive vias 180 electrically connects the trace patterns 160 of the first layer to the trace patterns 170 of the second layer. One end of each of the conductive vias 180 is connected to the trace pattern 160 of the first layer, and the other end thereof is connected to the trace pattern 170 of the second layer. The conductive vias 180 are conductive patterns penetrating substantially vertically through the base layer 110. The trace patterns 170 of the second layer may include fifth to eighth trace patterns 171, 172, 173, and 174. The first to eighth descriptions are for distinguishing the members, and are not used to limit the members themselves or to mean a specific order.

The ball lands 190 are electrically connected to the trace patterns 170 of the second layer, respectively. The trace patterns 170 of the second layer electrically connect the conductive vias 180 to the ball lands 190, respectively. The ball lands 190 are portions to which an outer connector (not shown) connecting the package substrate 100 to an external device is connected. The outer connector may include a solder ball.

Referring to FIGS. 2 and 3, the bonding finger 140 may be connected to the semiconductor chip 130 through an inner connector. For example, the fourth bonding finger 144 and the contact pad 131 of the semiconductor chip 130 are electrically connected to each other through a bonding wire 135. In FIG. 3, the inner connector is provided with a bonding wire 135, but the inner connector may include other types of conductive members. For example, the inner connector may be provided in the form of a conductive bump.

First plating layers 151 are formed on the surfaces of the bonding fingers 140, respectively. The first plating layer 151 may be formed of a layer which increases the adhesion between the bonding wire 135 and the bonding finger 140. The first plating layer 151 may be formed of a layer that improves the electrically conductivity between the bonding wire 135 and the bonding finger 140. When the bonding finger 140 is formed to include a copper (Cu) layer, the first plating layer 151 may be formed of a layer that prevents corrosion of the copper layer and prevents contamination. The first plating layer 151 is formed by an electrolytic plating process. The first plating layer 151 may include a conductive material constituting the bonding finger 140 and another conductive material such as nickel and gold (Ni / Au).

2 and 4 together, the second plating layer 152 is formed on the surface of the ball land 190. The second plating layer 152 prevents the ball land 190 from oxidizing and suppresses excessive formation of the intermetallic compound when the outer connector (not shown), that is, the solder ball is connected to the ball land 190. It can be formed in layers. When the first plating layer 151 is formed by an electroplating process, the second plating layer 152 may be electroplated at the same time. In another embodiment, the first plating layer 151 and the second plating layer 152 may be plated through a separate electrolytic plating process.

Referring back to FIG. 2, the first plating layer 151 and the second plating layer 152 are formed by an electroplating process. The electrolytic plating process requires applying a plating electrical current to the bonding fingers 140 and the ball lands 190. Through a plating line structure comprising a plating bus 129, a plating lead line 121, and temporary bridge lines 126, the plating current is applied to the bonding fingers 140 and the ball lands 190. Can be.

Referring to FIG. 3, the plating bus 129 is disposed in the boundary region 104 of the package substrate 100. The plating bus 129 is formed on the first surface 111 of the base layer 110 in the boundary region 104. The plating lead line 121 is in the form of a branched conductive line branched from the plating bus 129. The plating lead line 121 is a conductive line extending from the plating bus 129 and electrically connected to the second bonding finger 142. The plating lead line 121 is connected to the second trace pattern 162 and electrically connected to the second bonding finger 142 through the second trace pattern 162. Although not shown, in another embodiment, the plating lead line 121 may be directly connected to the second bonding finger 142.

The plating lead line 121 is connected only to the second bonding finger 142 among the various bonding fingers 140 on the first surface 111 of the base layer 110. The plating lead line 121 is disposed to be spaced apart from the first bonding finger 141 on the first surface 111 of the base layer 110. On the first surface 111 of the base layer 110, the plating lead line 121 is not directly connected to the first trace pattern 161 or the third and fourth trace patterns 163 and 164. On the first surface 111 of the base layer 110, the plating lead line 121 is not directly connected to the first bonding fingers 141 or the third and fourth bonding fingers 143 and 144.

The second bonding finger 142 and the second trace pattern 162 are some parts constituting a power line, for example. On the other hand, the first bonding finger 141 and the first trace pattern 161 and the third and fourth bonding fingers 143 and 144 and the third and fourth trace patterns 163 and 164 are formed of the signal lines. Some parts. The plating lead line 121 is connected to only the power line positioned on the first surface 111 of the base layer 110, and is not directly connected to the signal lines.

Referring to FIG. 2, the plating lead line 121 and the plating bus 129 are disposed on the first surface 111 of the base layer 110, while the temporary bridge lines 126 are formed of the base layer 110. It is disposed on the second surface 112. The plating lead lines 121 and the temporary bridge lines 126 are respectively located on opposite surfaces.

Referring to FIG. 4, the temporary bridge lines 126 electrically connect the conductive vias 190 spaced from each other. Temporary bridge lines 126 allow plating current to flow between conductive vias 190 spaced apart from one another. The temporary bridge lines 126 are provisional conductive lines that are electrically disconnected after the electrolytic plating process. The plating current applied to the plating inlet line 121 is connected to the first bonding fingers 141, the third and fourth bonding fingers 143 and 144 through the temporary bridge lines 126 and the conductive vias 180. Can be delivered to.

2 and 4, a fifth trace pattern 171 electrically connected to the first ball land 191 is provided on the second surface 112 of the base layer 110. The first ball land 191 is electrically connected to the first conductive via 181. The fifth trace pattern 171 is connected to the first conductive via 181 and is electrically connected to the first trace pattern 161 through the first conductive via 181. The first ball land 191 is electrically connected to the first bonding finger 141 via the fifth trace pattern 171, the first conductive via 181, and the first trace pattern 161. The first ball land 191, the fifth trace pattern 171, the first conductive via 181, the first trace pattern 161, and the first bonding fingers 141 provide a signal line.

The second ball land 192 is spaced apart from the first ball land 191. The second ball land 192 is electrically connected to the second conductive via 182. The first temporary bridge line 122 of the temporary bridge lines 126 electrically connects the second ball land 192 to the first ball land 191. The first temporary bridge line 122 electrically connects the fifth trace pattern 171 to the sixth trace pattern 172. The fifth trace pattern 171 electrically connects the first ball land 191 and the first conductive via 181. The sixth trace pattern 172 electrically connects the second ball land 192 and the second conductive via 182. The first borland 191 is electrically connected to the second borland 192 through the first temporary bridge line 122 and the fifth and sixth trace patterns 171 and 172. The first temporary bridge line 122 electrically connects the second conductive via 182 to the first conductive via 181. The second ball land 192, the sixth trace pattern 172, the second conductive via 182, the second trace pattern 162, and the second bonding fingers 142 may provide a power line.

The fifth and sixth trace patterns 171 and 172 are conductive lines spaced apart from each other on the second surface 112 of the base layer 110. The second conductive via 182 is spaced apart from the first conductive via 181. The second conductive via 182 is electrically connected to the plating lead-in line 121 at the first surface 111 of the base layer 110, and the first conductive via 181 is the first surface of the base layer 110. Electrically connected to the first bonding finger 141 at 111.

The first temporary bridge line 122 substantially connects the first conductive via 181 to the second conductive via 182. The first temporary bridge line 122 electrically connects the first bonding finger 141 and the first ball land 191 to the plating lead line 121. The plating current applied through the plating inlet line 121 is transmitted to the first bonding finger 141 and the first ball land 191 through the first temporary bridge line 122.

The plating current applied through the plating bus 129 may include a plating lead line 121, a second trace pattern 162, a second conductive via 182, a sixth trace pattern 172, and a first temporary bridge line ( 122, the conductive material is applied to the first bonding finger 141 through the conductive paths of the fifth trace pattern 171, the first conductive via 181, and the first trace pattern 161. Since a plating current is applied to the first bonding finger 141, the first plating layer 151 may be formed on the first bonding finger 141 by electroplating.

The plating current applied to the plating bus 129 may include the plating lead line 121, the second trace pattern 162, the second conductive via 182, the sixth trace pattern 172, and the first temporary bridge line 122. ) And the conductive path of the fifth trace pattern 171 are applied to the first ball land 191. When the plating current is applied to the first bonding finger 141 and the first ball land 191 at the same time, the first plating layer 151 and the second plating layer 152 are simultaneously bonded to the first bonding finger 141 and the first ball. The land 191 may be electroplated.

The plating current applied to the plating bus 129 passes through the conductive paths of the plating lead-in line 121, the second trace pattern 162, the second conductive via 182, and the sixth trace pattern 172. Applied to land 192. Since the second trace pattern 162 is connected to the second bonding finger 142, as shown in FIG. 3, a plating current is simultaneously applied to the second bonding finger 142. The first plating layer 151 is formed on the second bonding finger 142 by electroplating, and the second plating layer 152 is formed on the second ball land 192 at the same time.

3 and 4, the second temporary bridge line 123 may connect the plating lead line 121 to the third bonding finger 143 and the third ball land through the first temporary bridge line 122. 193) electrically. The second temporary bridge line 123 electrically connects the seventh trace pattern 173 and the third conductive via 183 connected thereto to the first temporary bridge line 122. In FIG. 4, the second temporary bridge line 123 is depicted as being directly connected to the first temporary bridge line 122, but in another embodiment, the second temporary bridge line 123 may be a first or second ball land ( 191, 192, or the fifth or sixth trace patterns 171, 172 may be modified to be directly connected to either.

The third temporary bridge line 124 connects the plating lead line 121 to the fourth bonding finger 144 and the fourth ball land 194 through the second and first temporary bridge lines 123 and 122. Electrically connected The third temporary bridge line 124 may be electrically connected to the first temporary bridge line 122 through the second temporary bridge line 123. Through the third temporary bridge line 124 and the second temporary bridge line 123, the fourth conductive via 184 may be electrically connected to the first temporary bridge line 122. An eighth trace pattern 174 and a fourth conductive via 184 connected thereto are electrically connected to the second temporary bridge line 123 through the third temporary bridge line 124.

The fourth temporary bridge line 125 connects the plating lead line 121 to another bonding finger 140 and another ball through the third, second and first temporary bridge lines 124, 123 and 122. It may extend to electrically connect the land 190.

As such, the temporary bridge lines 126 are introduced to electrically connect or connect the ball lands 190 spaced from each other. The first, third and fourth bonding fingers 141, 143, and 144 are not directly connected to the plating lead line 121 on the first surface 111 of the base layer 110. However, through the temporary bridge lines 126 and the conductive vias 180, the first, third and fourth bonding fingers 141, 143, 144 may be electrically connected to the plating lead line 121. have.

By the temporary bridge lines 126, additional plating lead lines other than the plating lead line 121 may be omitted from the first surface 111 of the base layer 110. In other words, the additional plating lead lines directly connecting the first, third and fourth bonding fingers 141, 143, and 144 and the plating bus 129 may be omitted.

The plating current is applied through the plating bus 129, the plating lead line 121, and the temporary bridge lines 126 to form the first plating layers 151 and the second plating layers 152 by electroplating. After forming the first plating layers 151 and the second plating layers 152, the temporary bridge lines 126 are cut off. That is, the temporary bridge line 126 is made into an electrical open state.

5 is a cross-sectional view schematically showing opening holes 117 provided in the package substrate 100 according to an exemplary embodiment. 6 is a plan view 116S schematically showing the opening holes 117 provided in the package substrate 100F according to one embodiment. FIG. 7 is a plan view schematically illustrating a top circuit wiring layout 101 of the package substrate 100F of FIG. 5.

5 through 7, after forming the first and second plating layers 151 and 152, the openings 117 may be formed by removing the middle portions 122C of the temporary bridge lines 126. Can be. The opening holes 117 may be formed in the bottom surface of the package substrate 100F. The bottom surface of the package substrate 100F is provided by the surface 116S of the second dielectric layer 116. The opening holes 117 are provided by the second dielectric layer 116. The opening holes 117 may be formed by an etching process that is performed on some regions of the second dielectric layer 116.

The opening hole 117 may be formed by removing a portion of the second dielectric layer 116 and thereby removing the middle portion 122C of the temporary bridge line 126 that is exposed. Wall surfaces of the first and second residual portions 122A and 122B of the temporary bridge lines 126 may be formed along the wall surfaces 117W of the opening hole 117. When the opening hole 117 removes the intermediate portion 122C connected to the first temporary bridge line 122 and the second temporary bridge line 123, the first temporary bridge along the wall surfaces 117W of the opening hole 117. Wall surfaces of the first and second residual portions 122A, 122B of the line 122 and the remaining portion 123A of the second temporary bridge line 123 are formed.

The opening hole 117 provided in the second dielectric layer 116 breaks the middle portion of the first temporary bridge line 122 and separates the remaining portions 122A and 122B from each other. The first residual portion 122A of the first temporary bridge line 122 and the other second residual portion 122B facing it are electrically spaced apart from each other and electrically separated from each other, thereby being in an electrically open state. . The opening hole 117 breaks the connection portion of the first temporary bridge line 122 and the second temporary bridge line 123 and separates the remaining portions 122A, 122B, and 123A from each other.

The ball lands 190 of FIG. 4 are electrically connected to each other by temporary bridge lines 126. 5 to 7, since the middle portion of the temporary bridge line 126 is broken while forming the opening hole 117 in the second dielectric layer 116, the ball lands 190 are electrically separated from each other. For example, the opening hole 117 electrically separates the first ball land 191 from the second to fourth ball lands 192, 193, and 194.

6 and 4, the first ball land 191 is connected to the first remaining portion 122A of the first temporary bridge line 122 through the fifth trace pattern 171. In addition, the second ball land 192 is connected to the second remaining portion 122B of the first temporary bridge line 122 through the sixth trace pattern 172.

6, 4, and 1, the second ball land 192 and the first ball land 191 may be a ball to which an operating voltage for operating the semiconductor chip 130 of the semiconductor package 10 is applied. It may be lands. The second ball land 192 and the first ball land 191 may be ball lands to which operating voltages of the same potential are applied. When the semiconductor chip 130 is operated, a signal voltage of, for example, 1.17 V is applied to the first ball land 191, and 1.17 V is applied to the first bonding finger 141 connected to the first ball land 191. Delivered. The electrical path from the first ball land 191 to the first bonding finger 141 may be, for example, a signal line to which a signal voltage of 1.17V is applied.

For example, a power voltage of 1.17 V may be applied to the second ball land 192. The electrical path from the second ball land 192 to the second bonding finger 142 may be a power line to which a power voltage of 1.17V is applied. A power voltage of 1.17 V equal to the signal voltage applied to the first ball land 191 may be applied to the second ball land 192. Operating voltages of substantially the same potential may be applied to the first ball land 191 and the second ball land 192. As shown in FIG. 4, the first temporary bridge line 122 may be electrically connected to the first ball land 191 and the second ball land 192 to which the same voltages are applied. Other power lines that apply voltages other than 1.17V or ground lines that are grounded to 0V are not connected to the first temporary bridge line 122.

8 is a plan view schematically illustrating a top circuit wiring layout 101-1 of the package substrate 100-1 according to an embodiment. FIG. 9 is a plan view schematically illustrating a bottom circuit wiring layout 102-1 of the package substrate 100-1 of FIG. 8. The same reference numerals as those shown in FIGS. 3 and 4 and FIGS. 6 and 7 in FIGS. 8 and 9 denote substantially the same members.

Referring to FIG. 8, the upper circuit wiring layout 101-1 of the package substrate 100-1 may include first and second plating lead lines 121 and 121-1 and first and second spaced apart from each other. A plated wire structure including a group of temporary bridge lines 126 and 126-1 is provided. The upper circuit wiring layout 101-1 further includes first and second groups of conductive lines 160 and 160-1.

The first and second plating lead lines 121 and 121-1 are spaced apart from each other and disposed on the first surface 111 of the base layer 110. The first plating lead line 121 may be connected to the first conductive line 162 which is one of the conductive lines 160 of the first group. The first conductive line 162 may be the same element as the second trace pattern 162 of FIG. 3. The conductive line 160 of the first group may be the same element as the trace patterns 160 of the first layer of FIG. 3. The first group of conductive lines 160 may further include a first trace pattern 161, a third trace pattern 163, and a fourth trace pattern 164.

The first group of bonding fingers 140 and the first group of conductive vias 180 may be connected to each of the first group of conductive lines 160. The bonding fingers 140 of the first group may be the same element as the bonding fingers 140 of FIG. 3. The first group of bonding fingers 140 may include a first bonding finger 141, a second bonding finger 142, a third bonding finger 143, and a fourth bonding finger 144. The conductive vias 180 of the first group may be the same element as the conductive vias 180 of FIG. 3. The first group of conductive vias 180 may include a first conductive via 181, a second conductive via 182, a third conductive via 183, and a fourth conductive via 184.

The second plating lead line 121-1 may be connected to the second conductive line 161-1, which is one of the conductive lines 160-1 of the second group. The second group of conductive lines 160-1 may include a second conductive line 161-1, a third conductive line 162-1, and a fourth conductive line 163-1. Each of the second group of conductive lines 160-1 may be connected with bonding fingers 140-1 of the second group and conductive vias 180-1 of the second group. The second group of bonding fingers 140-1 may include a fifth bonding finger 141-1, a sixth bonding finger 142-1, and a seventh bonding finger 143-1. The second group of conductive vias 180-1 may include a fifth conductive via 181-1, a sixth conductive via 182-1, and a seventh conductive via 183-1. The conductive lines 160 and 160-1 of the first and second groups are spaced apart from each other on the first surface 111 of the base layer 110.

Referring to FIG. 9, a plurality of third and fourth groups of conductive lines 170 and 170-1 are provided on the second surface 112 of the base layer 110. The plurality of temporary bridge lines 126 of the first group electrically connect the conductive lines 170 of the third group to each other. The conductive line 170 of the third group may be the same element as the trace patterns 170 of the second layer of FIG. 4. The third group of conductive lines 170 may include fifth, sixth, seventh, and eighth trace patterns 171, 172, 173, and 174. The plurality of temporary bridge lines 126-1 of the second group electrically connect the conductive lines 170-1 of the fourth group to each other. The fourth group of conductive lines 170-1 may include a fifth conductive line 171-1, a sixth conductive line 172-1, and a seventh conductive line 173-1.

The second dielectric layer 116 provides the first opening holes 117 and the second opening holes 117-1. The first opening hole 117 breaks the middle portion 122C of the first temporary bridge line 122, which is one of the temporary bridge lines 126 of the first group, to form the first and second residual portions 122A and 122B. ). The first opening hole 117 may also separate the remaining portion 123A of the second temporary bridge line 123 so as to be spaced apart from the first remaining portion 122A. The third opening hole 117-2 may be further spaced apart from the first opening hole 117.

The second opening hole 117-1 breaks the middle portion 122C-1 of the second temporary bridge line 122-1 of the second group, which is one of the temporary bridge lines 126-1 of the second group. The third and fourth remaining portions 122A-1 and 122B-1 are separated. In addition, the second opening hole 117-1 may separate the remaining portion 123A-1 of the second temporary bridge line 123-1 from the third residual portion 122A-1.

The first and second remaining portions 122A and 122B are conductive lines to which operating voltages of the same first potential are applied to each other. The same first potential operating voltages are applied to the first group of first ball lands 191 and the first group of second ball lands 192 connected to the first and second residual portions 122A and 122B, respectively. do. For example, the second remaining portion 122B is connected to a power line for applying power to the semiconductor chip 130, and the first remaining portion 122A is connected to the semiconductor chip 130 with data signals, address signals, or commander signals. Can be connected to a signal line for applying them.

The third and fourth remaining portions 122A-1 and 122B-1 are conductive lines to which operating voltages of the same second potential are applied to each other. The same as the first ball land 191-1 of the second group and the second ball land 192-1 of the second group connected to each of the third and fourth remaining portions 122A-1 and 122B-1. The operating voltages of the second potential are applied. For example, the third remaining portion 122A-1 may be connected to one first ground line connected to the semiconductor chip 130, and the fourth remaining portion 122B-1 may be connected to another second ground line. have.

The third group of conductive lines 170 and the fourth group of conductive lines 170-1 may be wires to which operating voltages of different potentials are applied. Accordingly, the first and second remaining portions 122A and 122B of the second temporary bridge line 122-1 of the second group may be formed by the third and fourth remaining portions 122A-1 and 122B-1. And wirings to which operating voltages of different potentials are respectively applied. The temporary bridge lines 126-1 of the second group electrically connect only wires to which voltages of the same potential are applied.

Referring back to FIG. 1, the package substrate 100F of the semiconductor package 10 includes the plating lead line 121 and the first and second residual portions 122A and 122B of the temporary bridge line 126.

1 and 7, the plating lead line 121 is limited to be connected only to the second conductive via 182 or the second bonding finger 142. In addition, as shown in FIGS. 6 and 7, in the process of forming the opening hole 117, since the intermediate portions 122C of the temporary bridge lines 126 are removed, the temporary bridge lines 126 may be electrically open. do.

Referring back to FIGS. 2 and 3, the package substrate 100 includes conductive lines of a plurality of first layers disposed on the first surface 111 of the base layer 110. The conductive lines of the first layer include trace patterns 160 and bonding fingers 140 of the first layer. 2 and 4, the package substrate 100 includes conductive lines of a plurality of second layers disposed on the second surface 112 of the base layer 110. The conductive lines of the second layer include the trace patterns 170 and the ball lands 190 of the second layer. The conductive lines of the plurality of second layers are electrically connected to the conductive lines of the first layer through the conductive vias 180, respectively. The plating lead line 121 is connected to the first trace pattern 161 which is the first conductive line among the conductive lines of the first layer. Temporary bridge lines 126 electrically connect the conductive lines of the second layer to each other.

The conductive line, for example, the second trace pattern 162 to which the plating lead line 121 is connected, may be provided as part of constituting a power line for applying power to the semiconductor chip 130. Alternatively, the second trace pattern 162 may be provided as part of constituting a signal line for applying a data signal to the semiconductor chip 130.

Referring to FIG. 5, the opening hole 117 of the second dielectric layer 116 is formed, thereby interrupting the middle portion of the first temporary bridge line 122 to form the first and second residual portions 122A and 122B. Can be separated into The first residual portion 122A is connected to the second conductive line of the conductive lines of the second layer, and the second residual portion 122B is connected to the third conductive line of the conductive lines of the second layer. The second conductive line may be exemplified by the fifth trace pattern 171. The third conductive line may be a sixth trace pattern 172. The second conductive line connected to the first residual portion 122A and the third conductive line connected to the second residual portion 122B respectively constitute wirings to which operating voltages of the same potential are applied.

The second conductive line provides a signal line for applying data signals, address signals, or commander signals to the semiconductor chip 130. The third conductive line provides a power line for applying power to the semiconductor chip 130. Alternatively, the second conductive line may provide a first ground line connected to the semiconductor chip 130, and the third conductive line may provide a second ground line that grounds the semiconductor chip 130.

10 is a cross-sectional view illustrating application of operating voltages V1 and V2 to the semiconductor package 10 according to an exemplary embodiment. FIG. 11 illustrates an example in which an electrochemical shift (ECM) defect 5119 is generated in the package substrate 10R of the comparative example.

Referring to FIG. 10, the semiconductor package 10 may be tested for reliability. One of the reliability tests is the Highly Accelerated Stress Test (HAST). A bias may be applied to the semiconductor package 10 at high temperature and high humidity to test the reliability of the semiconductor package 10. The bias may be given at voltages at substantially the same level as the operating voltages of the semiconductor package 10. For example, the first voltage V1 may be applied to the first ball land 191 of the semiconductor package 10, and the second voltage V2 may be applied to the second ball land 192. The first voltage V1 may be applied at approximately 1.17V as the power voltage VDD. The second voltage V2 may be applied at about 1.17V as the data signal voltage VDDQ. The first and second remaining portions 122A and 122B facing the opening hole 117 are connected to the first and second ball lands 191 and 192, respectively. Each of the first and second residual portions 122A and 122B may be applied with the same potential of 1.17V.

Sides of the first and second residual portions 122A and 122B are exposed to the opening hole 117 and are exposed to the HAST test environment. Since the same potential 1.17V is applied to the first and second residual portions 122A and 122B, the potential difference between the first and second residual portions 122A and 122B is theoretically OV. Since no potential difference is caused between the first and second residual portions 122A and 122B, the electrochemical shift (ECM) phenomenon between them can be suppressed.

Referring to FIG. 11, in the package substrate 10R of the comparative example, the first dielectric layer 5115 and the second dielectric layer 5116 are positioned above and below the base layer 5100. An opening hole 5117 may be formed in the second dielectric layer 5116 while breaking the temporary bridge line. Wall surfaces of the first residual portion 5122A and the second residual portion 5122B are exposed on the wall surface of the opening hole 5117. When the third voltage V3 and the fourth voltage V4 of different potentials are applied to the first residual portion 5122A and the second residual portion 5122B, the first residual portion 5122A and the second residual portion ( A potential difference other than 0 V is formed between 5122B). This potential difference may cause an electrochemical shift (ECM) phenomenon between the first residual portion 5122A and the second residual portion 5122B. Due to the EMC phenomenon, movement and precipitation of metal ions may occur between the first residual portion 5122A and the second residual portion 5122B. The movement and precipitation of the metal ions may generate a defective conductive layer 5119 between the first residual portion 5122A and the second residual portion 5122B. The defective conductive layer 5119 can cause a defect that electrically connects the first residual portion 5122A and the second residual portion 5122B. The defective conductive layer 5119 causes a failure of electrically connecting the first conductive line 5171 and the second conductive line 5152 electrically connected to the first residual portion 5122A and the second residual portion 5122B, respectively. can do.

Referring back to FIG. 10, since the same potential 1.17 V is applied to the first and second residual portions 122A and 122B, an electrochemical shift (ECM) between the first and second residual portions 122A and 122B is performed. The phenomenon can be suppressed. When HAST testing the semiconductor package 10, an ECM phenomenon may be prevented from occurring in the semiconductor package 10. Therefore, the reliability of the HAST result can be improved.

12 is a plan view illustrating a top circuit wiring layout 201 of a package substrate 200 according to an example. 13 is a plan view illustrating a top circuit wiring layout 301 of a package substrate 300 according to a comparative example.

The top circuit wiring layout 201 of the package substrate 200 shown in FIG. 12 shows circuit wirings disposed throughout the inner region 203. The plating lead lines 221-1, 221-2, and 221-3 are not directly connected to the first conductive lines 260S on the first surface 211 of the base layer of the package substrate 200. Is designed. The first conductive lines 260S may include signal lines for applying data signals or address and command signals to the semiconductor chip 230. The first conductive lines 260S include a first trace pattern 261-1, a first bonding finger 241-1, and a first conductive via 281.

The plating lead lines 221-1, 221-2, and 221-3 are arranged to be connected to non-signal lines, respectively. For example, the first plating lead-in line 221-1 is branched from the plating bus 229 and connected to the second conductive line 260P. The second conductive line 260P includes a second trace pattern 262-1, a second bonding finger 242-1, and a second conductive via 282. The second conductive line 260P provides a first power line for applying power to the semiconductor chip 230. Another second plating lead-in line 221-2 may be introduced to connect the plating bus 229 and the ground plane 262-2. The third plating lead-in line 221-3 may connect another second power line to the plating bus 229.

In the first surface 211 of the base layer of the package substrate 200 according to an embodiment, the plating lead lines 221-1, 221-2, and 221-3 are connected to only a few power lines or grounds. do. On the other hand, the top circuit wiring layout 301 of the package substrate 300 according to the comparison as shown in FIG. 13 shows that a very large number of plating lead lines 322 are branched from the plating bus 329. In the upper circuit wiring layout 301, plating lead lines 322 are connected to each of the signal lines 362 disposed to electrically connect with the semiconductor chip 330. As such, plating lead lines 322 are introduced in a very large number.

The plating lead lines 322 respectively connected to the signal lines 362 may serve as stubs, which are unnecessary transmission lines when the final product semiconductor package is operated. Accordingly, when applying or outputting a signal to the semiconductor chip 330, the plating lead lines 322 may act as a factor causing reflection of the signal or lowering the signal integrity of the semiconductor package.

The plating lead lines 221-1, 221-2, and 221-3 shown in FIG. 12 are introduced in a very small number compared to the plating lead lines 322 shown in FIG. 13. The total extension length of the plating lead lines 221-1, 221-2, and 221-3 may have a relatively shortened length. In addition, the plating lead lines 221-1, 221-2, and 221-3 of FIG. 12 are not connected to the signal lines 260S. Thus, the plating lead lines 221-1, 221-2, and 221-3 can effectively exclude the acting as a stub for the signal lines 260S.

As described above, embodiments of the present application are illustrated and illustrated in the drawings, but this is for explaining what is intended to be presented in the present application and is not intended to limit what is intended to be presented in the present application in a detailed form. Various other modifications will be possible so long as the technical spirit suggested in the present application is reflected.

100: package substrate,
117: opening hall,
121: plating lead-in line,
122A, 122B: residual portion of the temporary bridge line,
126: temporary bridge line,
140: bonding fingers,
151, 152: plating layer,
160: trace pattern of the first layer,
170: Trace pattern of the second layer.
180: conductive via,
190: conductive ball land.

Claims (19)

Semiconductor chips; And
And a package substrate on which the semiconductor chip is mounted.
The package substrate
A base layer comprising first and second surfaces opposing each other,
A first bonding finger disposed on the first surface of the base layer,
A plating lead line spaced apart from the first bonding finger on the first surface of the base layer,
A first conductive via electrically connected to the first bonding finger and substantially penetrating the base layer,
A second conductive via electrically connected to the plating inlet line and spaced apart from the first conductive via,
First and second ball lands that respectively connect to the first and second conductive vias at a second surface of the base layer,
A first provisional bridge line electrically connecting the first conductive via to the second conductive via at a second surface of the base layer, and
A dielectric layer covering a second surface of the base layer, the dielectric layer providing an opening hole that breaks an intermediate portion of the first temporary bridge line and separates the first and second residual portions spaced apart from each other;
And the first ball land electrically connected to the first remaining portion and the second ball land connected to the second residual portion are ball lands to which operating voltages of substantially the same potential are applied. The method of claim 1,
A first plating layer formed on the first bonding finger; And
And a second plating layer formed on the first and second ball lands. The method of claim 1,
The second conductive via, the first temporary bridge line and the first conductive via
And a path for electrically connecting the plating lead line to the first bonding finger. The method of claim 1,
Spaced apart from the first bonding finger at a first surface of the base layer,
And a second bonding finger electrically connected to the plating lead line. The method of claim 4, wherein
The second ball land, the second conductive via, and the second bonding finger may be
Providing a power line for applying power to the semiconductor chip,
The first ball land, the first conductive via, and the first bonding finger may be
And a signal line for applying data signals, address signals, or commander signals to the semiconductor chip. The method of claim 4, wherein
The first ball land, the first conductive via, and the first bonding finger may be
Providing a first ground line connected to the semiconductor chip,
And the second ball land, the second conductive via, and the second bonding finger provide a second ground line connected to the semiconductor chip. The method of claim 4, wherein
A first trace pattern connecting the first bonding finger to the first conductive via on a first surface of the base layer; And
And a second trace pattern spaced apart from the first trace pattern and connecting the second bonding finger to the second conductive via. The method of claim 7, wherein
Third and fourth bonding fingers spaced apart from the first and second bonding fingers at a first surface of the base layer;
Third and fourth conductive vias spaced apart from the first and second conductive vias; And
And third and fourth trace patterns connecting the third and fourth bonding fingers to the third and fourth conductive vias, respectively. The method of claim 8,
The package substrate
A second temporary bridge line electrically connecting the third conductive via to the first temporary bridge line,
The opening hole is
And a connecting portion connected to the first temporary bridge line of the second temporary bridge line together to separate the remaining portion of the second temporary bridge line so as to be spaced apart from the first and second residual portions. Semiconductor chips; And
And a package substrate on which the semiconductor chip is mounted.
The package substrate
A base layer comprising first and second surfaces opposing each other,
Conductive lines of a plurality of first layers disposed on a first surface of the base layer,
Conductive lines of a plurality of second layers disposed on the second surface of the base layer and electrically connected to the conductive lines of the first layer, respectively;
A plating lead line connected to a first conductive line of the conductive lines of the first layer,
A provisional bridge line electrically connecting the conductive lines of the second layer to each other, and
A dielectric layer covering a second surface of the base layer, the dielectric layer providing an opening hole that breaks an intermediate portion of the temporary bridge line and separates the first and second residual portions spaced apart from each other;
The second conductive line connected to the first remaining portion and the third conductive line connected to the second remaining portion of the conductive lines of the second layer are conductive lines to which operating voltages of substantially the same potential are applied. . The method of claim 10,
The second conductive line is
Providing a signal line for applying data signals, address signals, or commander signals to the semiconductor chip;
The third conductive line is
A semiconductor package providing a power line for applying power to the semiconductor chip. The method of claim 10,
The second conductive line is
Providing a first ground line connected to the semiconductor chip,
And the third conductive line provides a second ground line for grounding the semiconductor chip. The method of claim 10,
First plating layers formed on some portions of the conductive lines of the first layer; And
And second plating layers formed on some portions of the conductive lines of the second layer. Semiconductor chips; And
And a package substrate on which the semiconductor chip is mounted.
The package substrate
A base layer comprising first and second surfaces opposing each other,
A plurality of first group of conductive lines and a second group of conductive lines disposed on the first surface of the base layer,
A plurality of third and fourth groups of conductive lines disposed on a second surface of the base layer and electrically connected to the first and second groups of conductive lines, respectively;
A first plating lead line connected to a first conductive line of one of the conductive lines of the first group,
A second plating lead line connected to one second conductive line of the second group of conductive lines,
Provisional bridge lines of a first group electrically connecting the conductive lines of the third group to each other,
Temporary bridge lines of a second group electrically connecting the conductive lines of the fourth group to each other,
A first opening hole covering the second surface of the base layer and separating the middle portion of the temporary bridge lines of the first group to separate the first and second residual portions spaced apart from each other, and
A dielectric layer providing a second opening hole that breaks the middle portion of the second group of temporary bridge lines and separates them into third and fourth residual portions spaced apart from each other,
The first and second residual portions are conductive lines to which operating voltages of the same first potential are applied to each other.
And the third and fourth remaining portions are conductive lines to which operating voltages of the second potential different from the first potential are equally applied. The method of claim 14,
The first remaining portion is
A signal line for applying data signals, address signals, or commander signals to the semiconductor chip;
The second remaining portion
A semiconductor package connected to a power line for applying power to the semiconductor chip. The method of claim 14,
The third residual portion is
Connected to a first ground line connected to the semiconductor chip,
And the fourth remaining portion is connected to a second ground line that grounds the semiconductor chip. The method of claim 14,
The first remaining portion and the second remaining portion
A semiconductor package connected to power lines for applying power to the semiconductor chip. The method of claim 14,
The first remaining portion and the second remaining portion
And a semiconductor package connected to ground lines that ground the semiconductor chip. The method of claim 14,
And the first remaining portion and the second remaining portion are respectively connected to signal lines for applying signals to the semiconductor chip.

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