KR20080076578A - Storage on common structure liquid crystal display and its driving method - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, a storage on common that swings a common voltage applied through a storage line in a liquid crystal display to prevent a reliability defect caused by a residual DC voltage in the liquid crystal panel. The present invention relates to a structure liquid crystal display device and a driving method thereof.

To this end, in the embodiment of the present invention by swinging the storage voltage supplied to the storage line formed on the first substrate at a specific cycle, the continuous DC voltage is not applied to the storage line, thereby suppressing the reliability failure and It is effective to prevent smudges on the screen.

Description

LCD having Storage On Common structure and Driving method of the same}

1 is a block diagram showing a basic configuration of a general liquid crystal display device.

2 is a circuit diagram schematically illustrating a structure of a liquid crystal panel in a liquid crystal display having a storage on gate structure.

3A and 3B are circuit diagrams and plan views schematically illustrating a structure of a liquid crystal panel in an LCD having a storage on common structure.

4 is a waveform diagram illustrating a part of signals applied to a general storage on common structure liquid crystal display device.

5 is a block diagram showing the configuration of a liquid crystal display according to a preferred embodiment of the present invention.

FIG. 6 is a block diagram illustrating an example of a preferred structure of a storage voltage generator in the liquid crystal display of FIG. 5.

FIG. 7 is a waveform diagram schematically illustrating an input / output signal waveform of the storage voltage generator of FIG. 6.

8 is a waveform diagram schematically illustrating a common voltage, a storage voltage, and a shape of an image signal of a liquid crystal display according to an exemplary embodiment of the present invention.

<Brief description of the main parts of the drawing>

4: External System 10: Interface

120: liquid crystal panel 140: driving circuit portion

144: timing controller 146: gate driver

148: data driver 160: driving voltage generation unit

170: storage voltage generator

Vcom: Common Voltage Vstr: Storage Voltage

Vsync: Vertical Sync Signal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, a storage on common that swings a common voltage applied through a storage line in a liquid crystal display to prevent a reliability defect caused by a residual DC voltage in the liquid crystal panel. The present invention relates to a structure liquid crystal display device and a driving method thereof.

 A general liquid crystal display device has an image implementation principle using optical anisotropy and polarization property of liquid crystal. As is well known, a liquid crystal has a thin and long molecular structure and its optical anisotropy with different refractive indices depending on the arrangement direction depends on its size. It has a polarity that changes the direction of molecular arrangement.

Accordingly, the liquid crystal display device includes a liquid crystal panel in which a pair of substrates on which a transparent field generating electrode is formed on a surface facing each other with a liquid crystal layer interposed therebetween is bonded to each other and a driving circuit provided separately. By adjusting the arrangement direction of the liquid crystals according to the electric field size between the two field generating electrodes, the transmittance is different, and then, the light emitted from the backlight is passed through to allow the difference in the transmittance to be expressed to the outside. Display an image.

1 is a block diagram showing a basic configuration of a general liquid crystal display device.

Referring to FIG. 1, a liquid crystal panel 20 interposed between two substrates to display gray levels of an image according to the refractive index of the liquid crystal, and a liquid crystal panel according to control signals and data signals input from an external system 4. 20 and a driving voltage generation unit 60 for generating a driving voltage and supplying the driving voltage to the above-described components 20 and 40.

Hereinafter, with reference to the drawings in more detail as follows.

First, the interface 10 receives a data signal (RGB Data) and control signals (input clock, horizontal synchronization signal, vertical synchronization signal, data enable signal) input from an external system 4 such as a personal computer. It supplies to the drive circuit part 40.

The driving circuit unit 40 is composed of a plurality of driver integrated circuits, and controls the liquid crystal panel 20 by using a control signal and a data signal input through the interface 10 and displays a gray level of an image in response to the data signal. do.

The driving voltage generator 60 supplies the operating power of each component and generates and supplies a common voltage of the liquid crystal panel 20.

Here, the liquid crystal panel 20 includes a plurality of gate lines and data lines intersecting in a matrix form, a first substrate on which a thin film transistor and a pixel electrode are formed, and a second substrate having a common electrode. And a liquid crystal capacitor formed by the pixel electrode and the common electrode, a storage capacitor for maintaining the voltage of the liquid crystal capacitor for a predetermined period, and a liquid crystal layer interposed between the first and second substrates.

The storage capacitor may be classified into a storage on gate (SOG) structure and a storage on common (SOC) structure liquid crystal display device according to the configuration position of the storage capacitor. This will be described in more detail with reference to FIG. 3B.

2 is a circuit diagram schematically showing the structure of a liquid crystal panel in a liquid crystal display device having a storage on gate structure, and FIGS. 3A and 3B are schematic diagrams showing a structure of a liquid crystal panel in a liquid crystal display device having a storage on common structure; Top view.

2 and 3A, in the liquid crystal panel 20, a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm intersect each other on the first substrate to form a plurality of pixel regions P. As shown in FIG. In the pixel region P, a thin film transistor T, a liquid crystal capacitor CLC, and a storage capacitor Cst are formed.

The liquid crystal capacitor CLC includes a pixel electrode on the first substrate and a common electrode on the second substrate in one pixel region P, and the pixel electrode is a gate input through the gate lines GL1 to GLn. The image signal Vdata is applied according to the driving signal Vg, and the common electrode is applied with the common voltage Vcom directly from the driving voltage generation unit 60 of FIG. 1 to form an electric field.

Also, in the above structure, in the case of the storage on gate structure, as illustrated in FIG. 2, the storage capacitor Cst is controlled by the next gate line of the pixel region, that is, the first gate line GL1. In the case of the storage capacitor Cst connected to the thin film transistor T, a predetermined region of the second gate line GL2 is formed as one electrode, and in the case of the storage on common structure, as shown in FIG. 3A, The storage lines SL1 to SLk penetrate the liquid crystal pixels, and the storage capacitor Cst is formed using one region of the storage lines SL1 to SLk as one electrode.

In other words, the storage-on-gate structure uses a part of the n-th gate line as a storage electrode of the n- 1st pixel area, and the storage-on-common structure configures the storage electrode as a separate storage line. This has an excellent advantage.

Hereinafter, the storage on common structure will be described in more detail. As shown in FIG. 3B, gate lines GL1 to GLn are uniformly spaced on the first substrate 22 and arranged in rows, and the data lines ( DL1 to DLm) are regularly spaced apart in a row. The gate lines GL1 to GLn and the data lines DL1 to DLm are arranged in a matrix form, and the thin film transistor T and the pixel electrode 29 are formed at the intersections thereof, and one pixel region ( It is defined as P).

A plurality of storage lines SL1 to SLk are formed between the gate lines GL1 to GLn in parallel and uniformly spaced apart from the gate lines GL, and storage capacitors are formed in a predetermined region of the storage lines SL1 to SLk. (Cst) is formed. The pixel electrode (not shown) and the storage lines SL1 to SLk of the region where the storage lines SL1 to SLk are formed in the pixel area P as described above are over-insulated (not shown). It wraps and functions as a storage capacitor (Cst).

In the liquid crystal display having the storage on common structure described above, the common voltage Vcom is applied to the common electrode corresponding to the pixel electrode, and the storage voltage Vstr is applied to the storage lines SL1 to SLk.

FIG. 4 is a waveform diagram illustrating a part of signals applied to a general storage on common structure liquid crystal display, and the common voltage Vcom applied to the common electrode of the liquid crystal panel 20 of FIG. 3A is about 5V to 6V. It is a DC voltage, and the storage voltage Vstr applied to the storage lines SL1 to SLk in FIG. 3B is a DC voltage of 0V. The image signal Vdata applied to the pixel electrode is an AC voltage swinging in units of one frame based on the common voltage Vcom.

Here, the reason why the DC voltage is used as the common voltage Vcom and the storage voltage Vstr, and the AC voltage as the image signal Vdata is that if only DC voltage is continuously applied to the liquid crystal for a predetermined period of time, the liquid crystal deteriorates. This is because the quality of the image is reduced.

Accordingly, the image signal Vdata is swinged by one frame based on the common voltage Vcom to prevent the continuous voltage from being applied to the liquid crystal in one direction.

In this case, the common electrode is formed over the entire second substrate, and as described above, since the DC voltage is applied to the storage line, the DC voltage is continuously applied to the region where the pixel electrode and the storage line overlap a predetermined area. This may cause a defect and eventually cause a stain defect on the screen.

The present invention has been made to eliminate the above-mentioned stains, DC, which is continuously applied to the liquid crystal in the region where the storage line of the first substrate and the common electrode of the second substrate overlap in the liquid crystal display device having a storage on common structure It is an object of the present invention to provide a storage on common structure liquid crystal display device and a method of driving the same.

In order to achieve the above object, a storage on common structure liquid crystal display device according to an exemplary embodiment of the present invention includes a gate line and a data line defining a pixel region in which a plurality of pixels intersect, a thin film transistor provided in the pixel region, A liquid crystal panel comprising a liquid crystal capacitor and a storage line; A driving circuit unit receiving a control signal and a data signal from an interface directly connected to an external system to control the light transmittance of the liquid crystal capacitor; A storage voltage generator configured to supply an AC waveform storage voltage to the storage line; And a driving voltage generator for supplying a driving voltage of the liquid crystal panel, the driving circuit unit, and the storage voltage generating unit.

The storage line may be arranged in parallel with the gate line or the data line.

The driving circuit unit may include a timing controller configured to generate a driving control signal for driving the liquid crystal panel in response to the control signal and to rearrange the data signal in a form that the data driver can process; A gate driver turning on / off the thin film transistor through the gate line in response to the driving control signal; And a data driver for converting the data signal into an image signal corresponding to the driving control signal and supplying the image signal to the pixel area through the data line.

The storage voltage generator generates the storage voltage in synchronization with the control signal.

The storage voltage generation unit includes: an ASIC receiving the driving voltage of the driving voltage generation unit and generating an ASIC output signal of an AC waveform; And a level shifter for amplifying the ASIC output signal.

The ASIC signal is a signal swinging between a minimum of 0V and a maximum of 3.3V.

The level shifter receives the ASIC output signal and amplifies the signal from 0V to 12V.

The ASIC may generate the ASIC output signal in synchronization with a vertical synchronization signal Vsync, which is a signal indicating the beginning or the end of one screen of the control signals.

The storage voltage is characterized in that the phase change timing is included in a vertical blanking time, which is a time excluding the time that the image signal is input from the total time of driving one screen.

The storage voltage is characterized in that the half cycle is set to 120 frames or more when the voltage level swings from the initial state and passes through the positive and negative polarities once and then returns to the initial state.

In order to achieve the above object, a driving method of a storage on common structure liquid crystal display device according to an exemplary embodiment of the present invention includes a gate line and a data line defining a pixel region by crossing a plurality of thin films and a thin film provided in the pixel region. A liquid crystal panel comprising a transistor, a liquid crystal capacitor, and a storage line; A driving circuit unit which receives a control signal and a data signal from an interface directly connected to an external system and controls the light transmittance of the pixel region; A storage voltage generator configured to generate a storage voltage Vstr swinging with an AC waveform; And a driving voltage generator for supplying a driving voltage of the liquid crystal panel, the driving circuit unit, and the storage voltage generation unit, wherein the storage voltage generation unit is configured to drive the liquid crystal panel. Receiving a voltage; Generating the storage voltage (Vstr); And supplying the storage voltage Vstr to the storage line of the liquid crystal panel.

The generating of the storage voltage Vstr may include generating an ASIC output voltage of an AC waveform; Amplifying the ASIC output voltage.

The ASIC output voltage is a voltage swinging between a minimum of 0V and a maximum of 3.3V.

The amplifying the ASIC output voltage may include amplifying the ASIC output voltage with a voltage swinging between a minimum of 0V and a maximum of 12V.

Generating an ASIC output voltage of the AC waveform, Synchronizing the ASIC output voltage to a vertical synchronization signal (Vsync) of the control signal; And including a phase change timing of the ASIC output voltage within a vertical blanking time.

Hereinafter, a storage on common liquid crystal display and a driving method thereof according to the present invention will be described with reference to the accompanying drawings.

5 is a block diagram showing the configuration of a liquid crystal display according to a preferred embodiment of the present invention.

Referring to FIG. 5, a liquid crystal panel 120 interposed between two substrates to display gray levels of an image according to the refractive index of the liquid crystal, and a liquid crystal panel according to control signals and data signals input from an external system 4. The driving circuit unit 140 for controlling the refractive index of the liquid crystal interposed in the 120, the driving voltage generation unit 160 for generating a driving voltage and supplying the driving voltage to the above-described components 120 and 140, and the storage voltage Vstr. The storage voltage generation unit 170 to generate a.

Hereinafter, with reference to the drawings in more detail as follows.

First, the interface 10 receives a data signal (RGB Data) and control signals (input clock, horizontal synchronization signal, vertical synchronization signal, data enable signal) input from an external system 4 such as a personal computer. Supply to the driving circuit unit 140. As the interface 10, a low voltage differential signal (LVDS) interface and a transistor transistor logic (TTL) interface are widely used for data and control signal transmission from an external system 4.

The liquid crystal panel 120 may have the same structure as that of the liquid crystal panel of the general storage on common structure liquid crystal display, that is, shown in FIG. 3A. As an example, referring to FIG. 3A, a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm intersect on a first substrate to form a plurality of pixel regions P, and each pixel In the region P, a thin film transistor T, a liquid crystal capacitor CLC, and a storage capacitor Cst are formed.

In addition, separate storage lines SL1 to SLk penetrating the inside of the liquid crystal pixel are formed, and a storage capacitor Cst is formed using a predetermined region of the storage lines SL1 to SLk as one electrode.

Here, the storage lines SL1 to SLk are formed to cross the pixel electrode 29 in parallel with the gate lines GL1 to GLn as shown, or in a direction parallel to the data lines DL1 to DLn. The pixel electrode 29 may be formed around the pixel electrode 29.

Referring back to FIG. 5, the driving circuit unit 140 includes a timing controller 144, a gate, and a data driver 146 and 148.

The timing controller 144 uses a plurality of gate driver integrated circuits using control signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and the like, which are input through the interface 10. And a driving control signal for driving the gate driver 146 composed of the plurality of data drivers 148 and the data driver 148 composed of a plurality of data driver integrated circuits.

The driving control signal includes a gate output enable signal GOE, a gate shift clock signal GSC, a gate start pulse signal GSP for driving the gate driver 146, and the data driver 148. A source sampling clock signal SSC, a source start pulse signal SSP, a source output enable signal SOE, and the like for driving.

In addition, the timing controller 144 rearranges the data signal RGB data input through the interface 10 in a form that the data driver 148 can process and transmits the data signal to the data driver 148.

The gate driver 146 performs on / off control of the thin film transistor T arranged on the liquid crystal panel 120 in response to driving control signals input from the timing controller 144.

At the same time, the data driver 148 supplies the image signal Vdata to the liquid crystal panel 120 to control the rotation angle of the liquid crystal molecules.

More specifically, although not separately illustrated, the data driver 148 includes a reference voltage generation unit (not shown), and thus, a gamma (GAMMA) criterion of a digital to analog converter (DAC) used in the data driver 148. Generate voltages. The reference voltage generator (not shown) may be configured externally as a separate circuit from the data driver 148.

As a result, the data driver 148 selects gamma reference voltages corresponding to the input data signal RGB data in response to driving control signals input from the timing controller 144, and selects the selected gamma reference voltages as the image signal Vdata. ) Is applied to the pixel electrode connected to the thin film transistor (T).

The driving voltage generator 160 supplies operating power of each component, generates a common voltage Vcom of the DC waveform, and applies the generated voltage to the common electrode of the liquid crystal panel 120.

The storage voltage generator 170 generates an AC waveform storage voltage Vstr swinging at a specific period in synchronization with the control signal of the timing controller 144 and supplies the generated storage voltage Vstr to the liquid crystal panel 120.

Here, since the swing period of the storage voltage (Vstr) does not directly affect the quality of the image but is a problem when the voltage is maintained in one direction for a predetermined period, the swing period is determined at an appropriate period, which is a storage voltage (Vstr). When the voltage level of) starts to change from the initial state, goes through the positive and negative polarities once, and then returns to the initial state, the half cycle of this is over 2 seconds. It is preferable to set it to more than 120 frames in half period.

FIG. 6 is a block diagram illustrating an example of a preferred structure of a storage voltage generator in the liquid crystal display of FIG. 5.

The storage voltage generator 170 includes an application specific integrated circuit (ASIC) 172 that generates an AC voltage in synchronization with a specific control signal, and a level shifter 174.

More specifically, the ASIC 172 synchronizes with the vertical synchronization signal Vsync used in the timing controller 144 of FIG. 5 and determines the swing timing of the ASIC output signal within the vertical blanking time. .

Here, the vertical synchronization signal (Vsync) is a signal indicating the beginning or the end of one screen, the vertical blanking time (Vertical Blanking time) is the time except the time that the actual video signal is input from the total time of driving the screen to be. Therefore, in order to prevent the video signal from being affected by the swing of the storage voltage, when the ASIC output signal is generated, the storage voltage Vstr having the same swing period is vertically synchronized within the vertical blanking time. It is set to be synchronized with the signal Vsync.

In addition, the ASIC 172 is a signal that the ASIC output signal is set to 120 frames or more in a half cycle as described above, and swings within 0V to 3.3V, and swings based on a common voltage that is generally between 5V and 6V. Since it cannot be, the level shifter 174 is provided at the output stage.

The level shifter 174 receives the ASIC output signal, amplifies it to a signal swinging within 0V to 12V, and supplies it as a storage voltage Vstr to the liquid crystal panel 120 (FIG. 5).

In other words, the driving method of the storage voltage generation unit according to an embodiment of the present invention, the ASIC output swinging from 0V to 3.3V in synchronization with the control signal input from the driving voltage generation unit and the control signal input from the timing controller Generating a voltage and amplifying the ASIC output voltage from 0V to 12V.

Here, the control signal is a vertical synchronization signal (Vsync), and the ASIC output signal includes a step of setting more than 120 frames in half a period.

Hereinafter, a change in the signal waveform according to the operation of the storage voltage generator will be described with reference to FIG. 7.

FIG. 7 is a waveform diagram schematically illustrating an input / output signal waveform of the storage voltage generation unit of FIG. 6. Referring to the drawings, as described above, the ASIC output signal has an i frame having a half period, and the minimum and maximum values of the voltage level are 0 V, respectively. And 3.3V square wave signal.

In addition, the ASIC output signal is amplified by a square wave signal having the same period through the level shifter (174 of FIG. 6) and having a minimum value and a maximum value of 0V and 12V, respectively, which is a storage voltage Vstr, which is a liquid crystal panel. (120 in FIG. 5).

At this time, as described above, since the storage voltage Vstr is set to synchronize with the vertical synchronization signal Vsync and the half cycle is 120 frames, the phase change of the vertical synchronization signal Vsync is repeated about 120 times. This will change. Of course, the phase change timing of the storage voltage Vstr should be set within the vertical blanking time.

8 is a waveform diagram schematically illustrating a common voltage, a storage voltage, and an image signal of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in the drawing, in the liquid crystal display according to the preferred embodiment of the present invention, a storage voltage (Vstr) in which a common voltage (Vcom) of 5V, which is a DC waveform voltage signal, is applied, and a half cycle swings from 0V to 12V in an i frame. ) Is applied to swing the phase of the voltage applied to the liquid crystal in the region where the common electrode and the storage electrode overlap, thereby preventing the voltage in one direction from being continuously applied. Here, the video signal Vdata is applied in the same manner as in the prior art.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art various modifications and variations of the present invention without departing from the spirit and scope of the present invention described in the claims below I can understand that you can.

The storage on common structure liquid crystal display device and the driving method thereof according to the present invention as described above swing a storage voltage supplied to a storage line formed on a first substrate at a specific cycle so that a continuous DC voltage is applied to the storage line. By avoiding this, there is an effect that it is possible to suppress the poor reliability and to prevent the staining of the screen caused by this.

Claims (15)

A liquid crystal panel comprising a gate line and a data line crossing a plurality of pixel regions, a thin film transistor provided in the pixel region, a liquid crystal capacitor, and a storage line; A driving circuit unit receiving a control signal and a data signal from an interface directly connected to an external system to control the light transmittance of the liquid crystal capacitor; A storage voltage generator configured to supply an AC waveform storage voltage to the storage line; A driving voltage generation unit supplying a driving voltage of the liquid crystal panel, the driving circuit unit, and a storage voltage generation unit; Storage on common structure liquid crystal display comprising a. The method of claim 1, And the storage line is disposed in a direction parallel to the gate line or the data line. The method of claim 1, The driving circuit unit, A timing controller which generates a driving control signal for driving the liquid crystal panel in response to the control signal and rearranges the data signal into a form that the data driver can process;  A gate driver turning on / off the thin film transistor through the gate line in response to the driving control signal; A data driver converting the data signal into an image signal in response to the driving control signal and supplying the image signal to the pixel area through the data line; Storage on common structure liquid crystal display device, characterized in that consisting of. The method of claim 1, And the storage voltage generator is configured to generate the storage voltage in synchronization with the control signal. The method of claim 1, The storage voltage generation unit, An ASIC which receives the driving voltage of the driving voltage generator and generates an ASIC output signal of an AC waveform; A level shifter for amplifying the ASIC output signal Storage on common structure liquid crystal display comprising a. The method of claim 5, wherein And the ASIC signal swings between a minimum of 0V and a maximum of 3.3V. The method of claim 5, wherein And the level shifter receives the ASIC output signal and amplifies the signal from the minimum 0V to the maximum 12V. The method of claim 5, wherein And the ASIC generates the ASIC output signal in synchronization with a vertical synchronization signal (Vsync), which is a signal indicating the beginning or the end of one screen of the control signals. The method of claim 1, And the storage voltage is included in a vertical blanking time which is a time when a phase change timing is less than a time when the image signal is input from the total time of driving one screen. The method of claim 1, When the storage voltage is one cycle in which the voltage level swings from the initial state, passes through the positive and negative polarities once, and then returns to the initial state, the storage period is set to a half cycle at 120 frames or more. Common structure liquid crystal display device. A liquid crystal panel comprising a gate line and a data line crossing a plurality of pixel regions, a thin film transistor provided in the pixel region, a liquid crystal capacitor, and a storage line; A driving circuit unit which receives a control signal and a data signal from an interface directly connected to an external system and controls the light transmittance of the pixel region; A storage voltage generator configured to generate a storage voltage Vstr swinging with an AC waveform; A driving method of a storage on common structure liquid crystal display device, comprising: a liquid crystal panel, a driving circuit part, and a driving voltage generation part supplying a driving voltage of the storage voltage generation part; Receiving the driving voltage by the storage voltage generation unit; Generating the storage voltage (Vstr); Supplying the storage voltage Vstr to the storage line of the liquid crystal panel. Method of driving a storage on common structure liquid crystal display comprising a. The method of claim 11, Generating the storage voltage (Vstr), Generating an ASIC output voltage of an AC waveform; Amplifying the ASIC output voltage Method of driving a storage on common structure liquid crystal display comprising a. The method of claim 12, And the ASIC output voltage is a voltage swinging between a minimum of 0V and a maximum of 3.3V. The method of claim 12, The amplifying the ASIC output voltage may include amplifying the ASIC output voltage with a voltage swinging from a minimum of 0 V to a maximum of 12 V. 2. The method of claim 12, Generating the ASIC output voltage of the AC waveform, Synchronizing the ASIC output voltage to a vertical synchronization signal (Vsync) of the control signals; Allowing the phase change timing of the ASIC output voltage to be included in a vertical blanking time. Method of driving a storage on common structure liquid crystal display comprising a.

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