KR101887680B1 - Liquid crystal display - Google Patents

Abstract

A liquid crystal display according to an embodiment of the present invention is a liquid crystal display having a display panel in which a plurality of liquid crystal cells are formed, wherein the liquid crystal cells share the same data line and are adjacent to each other between the first gate line and the second gate line Forming a first pair in units of two liquid crystal cells arranged in a row; The two liquid crystal cells constituting the first pair include a first liquid crystal cell connected to the data line through a first TFT and a second liquid crystal cell connected to the data line through a second TFT and a third TFT and; The first TFT and the second TFT are turned on when the first gate line is activated by a scan signal, and the third TFT is turned on when the second gate line is activated by the scan signal.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device capable of increasing an aperture ratio.

The liquid crystal display displays an image by controlling the light transmittance of the liquid crystal layer through an electric field applied to the liquid crystal layer in accordance with a video signal. Such a liquid crystal display device is a flat panel display device having advantages of small size, thinness and low power consumption, and is used as a portable computer such as a notebook PC, office automation equipment, audio / video equipment and the like. Particularly, an active matrix type liquid crystal display device in which a switching element is formed for each liquid crystal cell is capable of actively controlling a switching element, which is advantageous for a moving image. A thin film transistor (hereinafter referred to as "TFT") is mainly used as a switching element used in this liquid crystal display device.

The liquid crystal display includes a plurality of liquid crystal cells for image implementation and signal lines for driving each of the liquid crystal cells. The signal lines include data lines to which a data voltage is applied and gate lines to which a scan signal is applied. As the resolution of the liquid crystal display increases, the number of data lines and gate lines increases. When an area where an image is displayed on a display panel of a liquid crystal display device is defined as an aperture area, the aperture ratio of the entire area of the display panel becomes the aperture ratio. Since image display is impossible in the region where the signal lines are formed, as the number of data lines and gate lines is increased, the aperture ratio is reduced accordingly. In addition, at a high resolution, when the number of data lines and gate lines is increased, the configuration of the driver circuit for driving the data lines and gate lines becomes complicated.

When m (m is a natural number equal to or greater than 2) liquid crystal cells are provided for each horizontal cell, a commonly known normal liquid crystal display device requires one gate line and m data lines to drive m liquid crystal cells . On the other hand, in order to simplify the structure of the data driving circuit, a liquid crystal display device of the DRD (Double Rate Driving) type, which is proposed, has two gate lines and m / 2 Data lines. The DRD driving method can reduce the number of output lines of the data driving circuit by reducing the number of data lines by half in comparison with the normal liquid crystal display at the same resolution. However, according to the DRD driving method, since the number of gate lines is doubled compared to the normal liquid crystal display at the same resolution, the number of signal lines as a whole increases rather. According to the DRD driving method, it is difficult to improve the aperture ratio of the display panel at a high resolution.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a liquid crystal display device capable of increasing the aperture ratio of a display panel while simplifying the structure of a driving circuit for driving signal lines of the display panel.

In order to achieve the above object, a liquid crystal display device according to an embodiment of the present invention is a liquid crystal display device having a display panel in which a plurality of liquid crystal cells are formed, wherein the liquid crystal cells share the same data line, A first pair of two liquid crystal cells arranged adjacent to each other between two gate lines; The two liquid crystal cells constituting the first pair include a first liquid crystal cell connected to the data line through a first TFT and a second liquid crystal cell connected to the data line through a second TFT and a third TFT and; The first TFT and the second TFT are turned on when the first gate line is activated by a scan signal, and the third TFT is turned on when the second gate line is activated by the scan signal.

The number of data lines is reduced by half compared with the number of liquid crystal cells in the horizontal direction or the number of data lines is reduced by the number of liquid crystal cells in the horizontal direction The number of gate lines can be reduced to about half of the number of liquid crystal cells in the vertical direction, thereby simplifying the structure of the driving circuit, and significantly increasing the aperture ratio.

1 is a view showing a liquid crystal display device according to an embodiment of the present invention.
2 illustrates a cell array according to an embodiment of the present invention.
3 is an equivalent circuit diagram showing a part of Fig.
FIG. 4 is a view showing a scan signal applied to the gate line of FIG. 3 and a data signal synchronized therewith; FIG.
5 is a view showing a cell array according to another embodiment of the present invention;
6 is an equivalent circuit diagram showing a part of Fig.
FIG. 7 is a view showing a scan signal applied to the gate line of FIG. 6 and a data signal synchronized therewith; FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 1 to 7. FIG.

1 shows a liquid crystal display according to an embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display device according to an embodiment of the present invention includes a display panel 10, a timing controller 11, a data driving circuit 12, and a gate driving circuit 13.

The display panel 10 includes two glass substrates and a liquid crystal layer formed therebetween. In the display panel 10, a plurality of liquid crystal cells Clc are arranged in a matrix form for each pixel region provided with an intersection structure of the data lines DL and the gate lines GL.

The lower glass substrate of the display panel 10 includes a plurality of data lines DL, a plurality of gate lines GL, TFTs, a pixel electrode 1 of a liquid crystal cell Clc connected to each TFT, A common electrode 2 and a storage capacitor Cst which are opposite to the electrodes 1 are formed. On the upper glass substrate of the display panel 10, a black matrix, a color filter, and the like are formed. The common electrode 2 is formed on an upper glass substrate in a vertical electric field driving mode such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. The common electrode 2 is formed of an IPS (In Plane Switching) mode, an FFS (Fringe Field Switching) Is formed on the lower glass substrate together with the pixel electrode 1 in the same horizontal electric field driving system. On the upper glass substrate and the lower glass substrate of the display panel 10, polarizing plates having optical axes orthogonal to each other are attached, and an alignment film for forming a pretilt angle of liquid crystal on the inner surface in contact with the liquid crystal is formed.

In the display panel 10, a cell array is formed according to the intersection structure of the data lines DL and the gate lines GL. The cell array includes a plurality of liquid crystal cells Clc. The liquid crystal cells Clc are paired in units of two adjacent liquid crystal cells. The two liquid crystal cells forming the pair share the same data line, so that the data voltage of the same polarity is charged.

The present invention has a cell array configuration as shown in Figs. 2 to 4, in order to reduce the number of data lines to nearly 1/2 of the required number at the corresponding resolution without substantially increasing the number of gate lines. In addition, the present invention has a cell array configuration as shown in Figs. 5 to 7, in order to reduce the number of data lines to nearly one half of the required number of the gate lines without increasing the number of data lines.

In each of these configurations, the two paired liquid crystal cells include a first liquid crystal cell connected to the data line through the first TFT and a second liquid crystal cell connected to the data line through the second TFT and the third TFT And the first gate line and the second gate line disposed adjacent to each other are allocated to the two liquid crystal cells in the pair. Further, in each of these configurations, the first TFT and the second TFT are turned on when the first gate line is activated by the scan signal, and the third TFT is turned on when the second gate line is activated by the scan signal. do.

The timing controller 11 receives a timing signal such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock signal DCLK, And generates control signals (DDC, GDC) for controlling the operation timing of the signal line (13).

The data control signal DDC for controlling the operation timing of the data driving circuit 12 includes a source sampling control signal for controlling the latch operation of data in the data driving circuit 12 based on a rising or falling edge, The source output enable signal SOE for controlling the output of the data driving circuit 12 and the polarity of the data voltage to be supplied to the liquid crystal cells Clc of the display panel 10 And a polarity control signal (POL) for controlling the signal.

The gate control signal GDC for controlling the operation timing of the gate driving circuit 13 includes a gate start pulse GSP indicating a starting horizontal line at which the scanning starts in one vertical period in which one screen is displayed, A gate shift clock signal (Gate Shift) generated in a pulse width corresponding to the ON period of the TFT as a timing control signal inputted to the shift register in the gate drive circuit 13 and sequentially shifting the gate start pulse GSP, Clock: GSC) and a gate output enable (GOE) for controlling the output of the gate driving circuit 13, and the like.

The timing controller 11 arranges the input digital video data RGB according to the resolution of the display panel 10 and supplies the data to the data driving circuit 12. [

The data driving circuit 12 includes a plurality of data drive ICs. Each of the data drive ICs includes a shift register, a latch, a digital to analog converter (DAC), an output buffer, and the like.

The data driving circuit 12 latches the digital video data RGB according to the data control signal DDC and converts the latched data into the positive data voltage or the negative data voltage with reference to the polarity control signal. The data driving circuit 12 inverts the polarity of the data voltage supplied to the data lines DL in units of data lines and inverts the data voltages in frame units. The data voltage whose polarity is inverted by the data driving circuit 12 is sequentially supplied to the data lines DL in synchronization with the scan signal.

The gate drive circuit 13 includes a plurality of gate drive ICs. Each of the gate drive ICs includes a shift register, a level shifter for converting an output signal of the shift register into a swing width appropriate for driving the TFT of the liquid crystal cell, and an output buffer. The gate driver circuit 13 generates a scan signal including two consecutive pulses in accordance with the gate control signal GDC and then supplies the generated scan signal to the gate lines GL in a line sequential manner, Select. The gate drive circuit 13 may be formed directly on the lower glass substrate together with the cell array by a GIP (Gate Driver In Panel) process.

2 shows a cell array according to an embodiment of the present invention. Fig. 3 shows an equivalent circuit for the part of Fig. 4 shows a scan signal applied to the gate line of FIG. 3 and a data signal synchronized with the scan signal.

Referring to FIGS. 2 and 3, the two liquid crystal cells paired in the cell array according to an embodiment of the present invention include a first liquid crystal cell LC1 and a second liquid crystal cell LC2, And a liquid crystal cell LC2. Since the first liquid crystal cell LC1 and the second liquid crystal cell LC2 are horizontally adjacent and connected to the same data line, one data line is allocated to each of the two vertical cells CL, Of the number of liquid crystal cells. Each of the gate lines is commonly connected to a part of the liquid crystal cell of the odd-numbered horizontal cell line (RL) and a part of the liquid crystal cell of the even-numbered horizontal cell line (RL), so that the number thereof is almost similar to the number of the liquid crystal cells in the vertical direction.

That is, according to an embodiment of the present invention, K (K is a positive even number) liquid crystal cells are formed along the extending direction of the gate lines for each horizontal cell line RL, (J / 2 + 1) data lines and (J + 1) gate lines are provided on the display panel when J (J is a positive even number) liquid crystal cells are formed along the extending direction of the line. For example, when sixteen liquid crystal cells are formed in each horizontal row line RL in FIG. 2 and three liquid crystal cells are formed in each vertical cell line CL, nine data lines Dm -1 to Dm + 7) and four gate lines (Gn to Gn + 3).

Referring to FIG. 3, the liquid crystal cells form a first pair in units of two liquid crystal cells disposed adjacent to each other between the first gate line Gn and the second gate line Gn + 1, And forms a second pair in units of two liquid crystal cells between the line Gn + 1 and the third gate line Gn + 2.

The first liquid crystal cell LC1 is connected to the data line Dm through the first TFT TR1 and the second liquid crystal cell LC2 is connected to the data line Dm through the second TFT TR2 and the third TFT TR3. (Dm). A first gate line Gn and a second gate line Gn + 1 are allocated to the upper and lower sides of the first and second liquid crystal cells LC1 and LC2, respectively.

The first TFT TR1 includes a gate electrode connected to the first gate line Gn, a drain electrode connected to the data line Dm, and a source electrode connected to the first liquid crystal cell LC1. The first TFT TR1 is turned on when the first gate line Gn is activated by the scan signal so that the data voltage charged in the data line Dm is applied to the first liquid crystal cell LC1.

The second TFT TR2 includes a gate electrode connected to the first gate line Gn, a drain electrode connected to the data line Dm, and a source electrode connected to the drain electrode of the third TFT TR3. The third TFT TR3 has a gate electrode connected to the second gate line Gn, a drain electrode connected to the source electrode of the second TFT TR2, and a source electrode connected to the second liquid crystal cell LC2. . The second and third TFTs TR2 and TR3 are turned on when the first and second gate lines Gn and Gn + 1 are simultaneously activated by the scan signal, so that the data voltage charged in the data line Dm is 2 liquid crystal cell LC2.

The third liquid crystal cell LC3 is connected to the data line Dm through the fourth TFT TR4 and the fourth liquid crystal cell LC4 is connected to the data line Dm through the fifth TFT TR5 and the sixth TFT TR6. (Dm). A second gate line Gn + 1 and a third gate line Gn + 2 are allocated to the upper and lower sides of the third and fourth liquid crystal cells LC3 and LC4, respectively.

The fourth TFT TR4 includes a gate electrode connected to the second gate line Gn + 1, a drain electrode connected to the data line Dm, and a source electrode connected to the third liquid crystal cell LC3. The fourth TFT TR4 is turned on when the second gate line Gn + 1 is activated by the scan signal so that the data voltage charged in the data line Dm is applied to the third liquid crystal cell LC3.

The fifth TFT TR5 includes a gate electrode connected to the second gate line Gn + 1, a drain electrode connected to the data line Dm, and a source electrode connected to the drain electrode of the sixth TFT TR6 do. The sixth TFT TR6 is connected to the gate electrode connected to the third gate line Gn + 2, the drain electrode connected to the source electrode of the fifth TFT TR5, and the drain electrode connected to the fourth liquid crystal cell LC4 Source electrode. The fifth and sixth TFTs TR5 and TR6 are turned on when the second and third gate lines Gn + 1 and Gn + 2 are simultaneously activated by the scan signal to turn on the data voltage Dm Is applied to the fourth liquid crystal cell LC4.

The scan signal SP applied to each gate line Gn, Gn + 1, and Gn + 2 is composed of two pulses as shown in FIG. The scan signal SP has a first pulse P1 having a first width A and a second pulse P1 having a second width B which is generated subsequent to the first pulse P1 and wider than the first width A. [ And a pulse P2.

The scan signal SPn of the second pulse P2 applied to the first gate line Gn is applied to the scan signal SPn of the first pulse P1 applied to the second gate line Gn + +1). In other words, the scan signal SPn of the second pulse P2 applied to the first gate line Gn and the scan signal SPn of the first pulse P1 applied to the second gate line Gn + 1) are overlapped by the first width (A). The rising edge of the second pulse P2 of the scan signal SPn and the rising edge of the first pulse P1 of the scan signal SPn + 1 may be synchronized with each other. The rising edge of the second pulse P2 of the scan signal SPn and the rising edge of the second pulse P2 of the scan signal SPn + 1 may be synchronized with each other.

As shown in FIG. 4, the scan signal SPn + 1 of the second pulse P2 applied to the second gate line Gn + 1 is applied to the first gate line Gn + The scan signal SPn + 2 is superimposed. In other words, the scan signal SPn + 1 of the second pulse P2 applied to the second gate line Gn + 1 and the first pulse P1 applied to the third gate line Gn + The signal SPn + 2 is overlapped by the first width A. The rising edge of the second pulse P2 of the scan signal SPn + 1 and the rising edge of the first pulse P1 of the scan signal SPn + 2 may be synchronized with each other. The second pulse P2 of the scan signal SPn + 1 and the rising edge of the second pulse P2 of the scan signal SPn + 2 may be synchronized with each other.

The data voltage DLC2 is applied to the second liquid crystal cell LC2 in a period T1 in which the scan signal SPn of the second pulse P2 and the scan signal SPn + Is charged. In this overlap period T1, the first liquid crystal cell LC1 and the third liquid crystal cell LC3 are precharged to the data voltage DLC2. The first liquid crystal cell LC1 is turned on during a period T2 in which the scan signal SPn of the second pulse P2 is not overlapped with the scan signal SPn + 1 of the first pulse P1, ).

In the period T3 during which the scan signal SPn + 1 of the second pulse P2 and the scan signal SPn + 2 of the first pulse P1 overlap in FIG. 4, the data voltage (DLC4) is charged. In this overlap period T3, the third liquid crystal cell LC3 is precharged to the data voltage DLC4. In the period T4 during which the scan signal SPn + 1 of the second pulse P2 is not overlapped with the scan signal SPn + 2 of the first pulse P1 in the third liquid crystal cell LC3, (DLC3).

The liquid crystal cells LC2 and LC4 for charging the data voltage through the two TFTs are longer in the charging path than the liquid crystal cells LC1 and LC3 for charging the data voltage through one TFT) Falls. The charging time for the second and fourth liquid crystal cells LC2 and LC4 must be increased as compared with that of the first and third liquid crystal cells LC1 and LC3 in order to compensate the difference in charging power between the liquid crystal cells. The width A of the first pulse P1 corresponding to the overlap period T1 is set to be wider than 1/2 of the width B of the second pulse P2.

In order to reduce the power consumption of the data driving circuit, the paired liquid crystal cells are zigzag-connected to the data lines along the vertical direction as shown in FIG. In other words, each of the two liquid crystal cells constituting the first pair in the odd-numbered horizontal cell line (RL) is connected to the data line arranged on either the left or right side thereof, and in the even-numbered horizontal cell line (RL) And each of the two liquid crystal cells forming the second pair is connected to a data line arranged on the other of the left and right sides of the two liquid crystal cells.

As a result, the liquid crystal cells connected to the data line through one TFT and the liquid crystal cells connected to the data line through the two TFTs are arranged in a check board type to mitigate the recognition of the luminance deviation between the liquid crystal cells .

As described above, the number of the data lines can be reduced to about half of the number of the liquid crystal cells in the horizontal direction while the number of gate lines is almost equal to the number of liquid crystal cells in the vertical direction, The aperture ratio can be greatly increased, as well as being simplified.

 5 shows a cell array according to another embodiment of the present invention. 6 shows an equivalent circuit for the part of Fig. 7 shows a scan signal applied to the gate line of FIG. 6 and a data signal synchronized with the scan signal.

Referring to FIGS. 5 and 6, the two liquid crystal cells paired in the cell array according to another embodiment of the present invention include a first liquid crystal cell LC1 'vertically adjacent to the extending direction of the data line, 2 liquid crystal cell LC2 '. Since the first liquid crystal cell LC1 'and the second liquid crystal cell LC2' are vertically adjacent and connected to the same data line, one gate line is allocated to each of the two horizontal cells RL, The number of liquid crystal cells in the vertical direction is reduced by about half. Each of the gate lines is commonly connected to a part of the liquid crystal cell of the odd-numbered horizontal cell line (RL) and a part of the liquid crystal cell of the even-numbered horizontal cell line (RL).

That is, according to another embodiment of the present invention, K (K is a positive even number) liquid crystal cells are formed along the extending direction of the gate line for each horizontal cell line RL, When (J is a positive even number) liquid crystal cells are formed along the extending direction of the line, (K + 1) data lines and (J / 2 + 1) gate lines are provided on the display panel. For example, when eight liquid crystal cells are formed for each horizontal line RL in FIG. 5 and four liquid crystal cells are formed for each vertical cell line CL, nine display lines Dm -1 to Dm + 7), and three gate lines (Gn to Gn + 2).

Referring to FIG. 6, the liquid crystal cells form a first pair in units of two liquid crystal cells disposed adjacent to each other between the first gate line Gn and the second gate line Gn + 1, And forms a second pair in units of two liquid crystal cells between the line Gn + 1 and the third gate line Gn + 2.

The first liquid crystal cell LC1 'is connected to the data line Dm through the first TFT TR1', the second liquid crystal cell LC2 'is connected to the second TFT TR2' and the third TFT TR3 ' To the data line Dm. A first gate line Gn and a second gate line Gn + 1 are allocated to the upper and lower sides of the first and second liquid crystal cells LC1 'and LC2', respectively.

The first TFT TR1 'includes a gate electrode connected to the first gate line Gn, a drain electrode connected to the data line Dm, and a source electrode connected to the first liquid crystal cell LC1'. The first TFT TR1 'is turned on when the first gate line Gn is activated by the scan signal so that the data voltage charged in the data line Dm is applied to the first liquid crystal cell LC1'.

The second TFT TR2 'includes a gate electrode connected to the first gate line Gn, a drain electrode connected to the data line Dm, and a source electrode connected to the drain electrode of the third TFT TR3' do. The third TFT TR3 'is connected to the gate electrode connected to the second gate line Gn, the drain electrode connected to the source electrode of the second TFT TR2', and the drain electrode connected to the second liquid crystal cell LC2 ' Lt; / RTI > source electrode. The second and third TFTs TR2 'and TR3' are turned on when the first and second gate lines Gn and Gn + 1 are simultaneously activated by the scan signal, Is applied to the second liquid crystal cell LC2 '.

The third liquid crystal cell LC3 'is connected to the data line Dm through the fourth TFT TR4', the fourth liquid crystal cell LC4 'is connected to the fifth TFT TR5' and the sixth TFT TR6 ' To the data line Dm. A second gate line Gn + 1 and a third gate line Gn + 2 are allocated to the upper and lower sides of the third and fourth liquid crystal cells LC3 'and LC4', respectively.

The fourth TFT TR4 'includes a gate electrode connected to the second gate line Gn + 1, a drain electrode connected to the data line Dm, and a source electrode connected to the third liquid crystal cell LC3' do. The fourth TFT TR4 'is turned on when the second gate line Gn + 1 is activated by the scan signal so that the data voltage charged in the data line Dm is applied to the third liquid crystal cell LC3' do.

The fifth TFT TR5 'includes a gate electrode connected to the second gate line Gn + 1, a drain electrode connected to the data line Dm, and a source electrode connected to the drain electrode of the sixth TFT TR6' . The sixth TFT TR6 'includes a gate electrode connected to the third gate line Gn + 2, a drain electrode connected to the source electrode of the fifth TFT TR5', and a fourth electrode connected to the fourth liquid crystal cell LC4 ' And a source electrode connected to the source electrode. The fifth and sixth TFTs TR5 'and TR6' are turned on when the second and third gate lines Gn + 1 and Gn + 2 are simultaneously activated by the scan signal, So that the data voltage is applied to the fourth liquid crystal cell LC4 '.

The scan signal SP applied to each gate line Gn, Gn + 1, and Gn + 2 is composed of two pulses as shown in FIG. The scan signal SP has a first pulse P1 having a first width A and a second pulse P1 having a second width B which is generated subsequent to the first pulse P1 and wider than the first width A. [ And a pulse P2.

The scan signal SPn of the second pulse P2 applied to the first gate line Gn is the scan signal SPn of the first pulse P1 applied to the second gate line Gn + +1). In other words, the scan signal SPn of the second pulse P2 applied to the first gate line Gn and the scan signal SPn of the first pulse P1 applied to the second gate line Gn + 1) are overlapped by the first width (A). The rising edge of the second pulse P2 of the scan signal SPn and the rising edge of the first pulse P1 of the scan signal SPn + 1 may be synchronized with each other. The rising edge of the second pulse P2 of the scan signal SPn and the rising edge of the second pulse P2 of the scan signal SPn + 1 may be synchronized with each other.

As shown in FIG. 7, the scan signal SPn + 1 of the second pulse P2 applied to the second gate line Gn + 1 is applied to the first pulse P1 (Pn + 1) applied to the third gate line Gn + The scan signal SPn + 2 is superimposed. In other words, the scan signal SPn + 1 of the second pulse P2 applied to the second gate line Gn + 1 and the first pulse P1 applied to the third gate line Gn + The signal SPn + 2 is overlapped by the first width A. The rising edge of the second pulse P2 of the scan signal SPn + 1 and the rising edge of the first pulse P1 of the scan signal SPn + 2 may be synchronized with each other. The second pulse P2 of the scan signal SPn + 1 and the rising edge of the second pulse P2 of the scan signal SPn + 2 may be synchronized with each other.

In the period T1 in which the scan signal SPn of the second pulse P2 and the scan signal SPn + 1 of the first pulse P1 overlap each other in FIG. 7, the second liquid crystal cell LC2 ' DLC2 'are charged. In this overlapping period T1, the first liquid crystal cell LC1 'and the third liquid crystal cell LC3' are precharged to the data voltage DLC2 '. The first liquid crystal cell LC1 'is turned on during a period T2 in which the scan signal SPn of the second pulse P2 is not overlapped with the scan signal SPn + 1 of the first pulse P1 DLC1 '.

In the period T3 in which the scan signal SPn + 1 of the second pulse P2 and the scan signal SPn + 2 of the first pulse P1 are superimposed on each other in the fourth liquid crystal cell LC4 ' The voltage DLC4 'is charged. In this overlap period T3, the third liquid crystal cell LC3 'is precharged to the data voltage DLC4'. In the period T4 during which the scan signal SPn + 1 of the second pulse P2 is not overlapped with the scan signal SPn + 2 of the first pulse P1, the third liquid crystal cell LC3 ' And charged with voltage DLC3 '.

The liquid crystal cells LC2 'and LC4' for charging the data voltage through the two TFTs are longer in the charging path than the liquid crystal cells LC1 'and LC3' for charging the data voltage through one TFT) The charging power drops. The charging time for the second and fourth liquid crystal cells LC2 'and LC4' must be increased as compared with that of the first and third liquid crystal cells LC1 'and LC3' in order to compensate the difference in the charging power between the liquid crystal cells. The width A of the first pulse P1 corresponding to the overlap period T1 is set to be wider than 1/2 of the width B of the second pulse P2.

In order to reduce the power consumption of the data driving circuit, the paired liquid crystal cells are zigzag-connected to the data lines along the vertical direction as shown in FIG. In other words, when a pair of horizontal cells is formed for each of the vertically adjacent two horizontal cells, each of the two liquid crystal cells forming the first pair in the odd-numbered horizontal cell array is connected to either the left side or the right side And each of the two liquid crystal cells constituting the second pair in the pair of the even-numbered horizontal cell lines is connected to the data line arranged on the other of the left and right sides thereof.

As a result, the liquid crystal cells connected to the data line through one TFT and the liquid crystal cells connected to the data line through the two TFTs are arranged in a stripe type, respectively.

As described above, according to another embodiment of the present invention, the number of data lines can be made substantially equal to the number of liquid crystal cells in the horizontal direction, and the number of gate lines can be reduced by half compared with the number of liquid crystal cells in the vertical direction. The aperture ratio can be greatly increased, as well as being simplified.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: data driving circuit 13: gate driving circuit

Claims (17)

1. A liquid crystal display device having a display panel in which a plurality of liquid crystal cells are formed,
The liquid crystal cells share a same data line and form a first pair in units of two liquid crystal cells disposed adjacent to each other between the first gate line and the second gate line;
The two liquid crystal cells constituting the first pair are,
A first liquid crystal cell connected to the data line through a first TFT and a second liquid crystal cell connected to the data line through a second TFT and a third TFT;
The first TFT and the second TFT are turned on when the first gate line is activated by the scan signal and the third TFT is turned on when the second gate line is activated by the scan signal,
The first liquid crystal cell is charged along a first data voltage charging path during a first data voltage charging time and the second liquid crystal cell is charged along a second data voltage charging path during a second data voltage charging time,
The second data voltage charging path is longer than the first data voltage charging path,
And the second data voltage charging time is longer than the first data voltage charging time. The method according to claim 1,
Wherein the scan signal comprises a first pulse having a first width and a second pulse subsequent to the first pulse and having a second width greater than the first width;
Wherein the scan signal of the second pulse applied to the first gate line overlaps the scan signal of the first pulse applied to the second gate line. 3. The method of claim 2,
Wherein a scan signal of the second pulse applied to the first gate line and a scan signal of the first pulse applied to the second gate line are overlapped with each other by the first width. 3. The method of claim 2,
Wherein the first width is larger than 1/2 of the second width. The method according to claim 1,
And a third gate line facing the first gate line with the second gate line interposed therebetween,
Between the second gate line and the third gate line, the liquid crystal cells form a second pair in units of two liquid crystal cells;
The two liquid crystal cells forming the second pair include a third liquid crystal cell connected to the data line through a fourth TFT and a fourth liquid crystal cell connected to the data line through a fifth TFT and a sixth TFT and;
The fourth TFT and the fifth TFT are turned on when the second gate line is activated by a scan signal, and the sixth TFT is turned on when the third gate line is activated by the scan signal. . 6. The method of claim 5,
The first liquid crystal cell and the second liquid crystal cell forming the first pair are horizontally adjacent to each other along the extending direction of the gate line;
And the third liquid crystal cell and the fourth liquid crystal cell forming the second pair are horizontally adjacent to each other along the extending direction of the gate line. The method according to claim 6,
(K is a positive even number) liquid crystal cells are formed along the extending direction of the gate lines for each horizontal cell, and J (J is a positive even number) liquid crystal cells Lt; / RTI >
Wherein the display panel is provided with (K / 2 + 1) data lines and (J + 1) gate lines. 8. The method of claim 7,
Wherein in the odd-numbered horizontal cell, each of the two liquid crystal cells forming the first pair is connected to a data line arranged on either the left or right side thereof;
And each of the two liquid crystal cells forming the second pair in the odd-numbered horizontal cell is connected to a data line disposed on the other of the left and right sides of the two liquid crystal cells. 9. The method of claim 8,
In the display panel,
Wherein the liquid crystal cells connected to the data line through one TFT and the liquid crystal cells connected to the data line through the two TFTs are arranged in a check board type. 6. The method of claim 5,
The first liquid crystal cell and the second liquid crystal cell forming the first pair are vertically adjacent to each other along the extending direction of the data line;
And the third liquid crystal cell and the fourth liquid crystal cell forming the second pair are vertically adjacent to each other along the extending direction of the data line. 11. The method of claim 10,
(K is a positive even number) liquid crystal cells are formed along the extending direction of the gate lines for each horizontal cell, and J (J is a positive even number) liquid crystal cells Lt; / RTI >
Wherein the display panel is provided with (K + 1) data lines and (J / 2 + 1) gate lines. 11. The method of claim 10,
When forming a pair of horizontal cells for each of the two vertically adjacent horizontal cells,
Each of the two liquid crystal cells forming the first pair in an odd-numbered horizontal cell array pair is connected to a data line arranged on either the left or right side thereof;
And each of the two liquid crystal cells constituting the second pair is connected to a data line arranged on the other one of the left and right sides of the pair of right and left horizontal cells. 13. The method of claim 12,
In the display panel,
Wherein the liquid crystal cells connected to the data line through one TFT and the liquid crystal cells connected to the data line through the two TFTs are arranged in a stripe type. The method according to claim 1,
A data voltage having a polarity inverted with respect to a frame period is applied to the data lines formed on the display panel,
And polarities of data voltages applied to neighboring data lines are opposite to each other. delete delete 6. The method of claim 5,
The third liquid crystal cell is charged along the third data voltage charging path during the third data voltage charging time and the fourth liquid crystal cell is charged along the fourth data voltage charging path during the fourth data voltage charging time,
The fourth data voltage charging path is longer than the third data voltage charging path,
And the fourth data voltage charging time is longer than the third data voltage charging time.

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